To use CSN hardware control, set register PSEL.CSN according to the Pin configuration.
Hardware-controlled CSN is suited when there is a single slave on the bus. When multiple slaves are attached to the bus, CSN must be controlled using GPIO.
When enabled, CSN is asserted automatically after TASKS_START is triggered, and deasserted after EVENTS_END. The value in register IFTIMING.CSNDUR sets the time between the falling edge of CSN and the first SCK edge. The same delay is used between the last SCK edge and the rising edge of CSN at the end of a transfer. It is also used between two transfers as the minimum CSN inactive time when the END_START short is enabled. The IFTIMING.CSNDUR is expressed in number of SPIM core clock periods.
The following figure shows a timing diagram with two SPI transmissions where the delay is controlled by IFTIMING.CSNDUR and is represented by tCSNDUR.
The following figure shows the timing delay for the combinations of polarity and phase settings. The register CSNPOL determines the active polarity of the signal.