In addition to the frame sync (FSYNC) pulse, TDM has two clock signals. The master clock MCK and the sample data bit clock SCK.
MCK and SCK are independent and can be configured individually.
The serial clock (SCK), often referred to as the serial bit clock, pulses once for each data bit being transferred on the serial data lines SDIN and SDOUT.
The polarity of SCK is configured in CONFIG.SCK.POLARITY.
When operating in Master mode, SCK clock source and frequency and is configured in CONFIG.SCK.SRC and CONFIG.SCK.DIV respectively. For CONFIG.SCK.DIV value, see Clock divider equations.
When operating in Slave mode, SCK is an input signal provided by the external master.
The optional master clock (MCK) is independent from SCK and FSYNC.
The master clock generator is enabled/disabled using CONFIG.MCK.EN, and the generator is started or stopped by the START or STOP tasks respectively.