TWIS slave timing specifications

nRF54LM20A | nRF54LM20B Datasheet

Symbol Description Min. Typ. Max. Units
fTWIS,SCL

Bit rates for TWIS16

100 400 kbps
tTWIS,START

Time from PREPARERX/PREPARETX task to ready to receive/transmit

1.5 µs
tTWIS,SU_DATI

Input data setup time before positive edge on SCL – all modes

20 ns
tTWIS,HD_DATI

Input data hold time after negative edge on SCL – all modes

0 ns
tTWIS,HD_DATO

Output data hold time after negative edge on SCL – all modes

350 600 ns
tTWIS,HD_STA,100kbps

TWI slave hold time from for START condition (SDA low to SCL low), 100 kbps

500 ns
tTWIS,HD_STA,400kbps

TWI slave hold time from for START condition (SDA low to SCL low), 400 kbps

500 ns
tTWIS,SU_STO,100kbps

TWI slave setup time from SCL high to STOP condition, 100 kbps

500 ns
tTWIS,SU_STO,400kbps

TWI slave setup time from SCL high to STOP condition, 400 kbps

500 ns
tTWIS,BUF,100kbps

TWI slave bus free time between STOP and START conditions, 100 kbps

500 ns
tTWIS,BUF,400kbps

TWI slave bus free time between STOP and START conditions, 400 kbps

500 ns
Figure 20. TWIS timing diagram, 1 byte transaction
TWIS timing diagram, 1 byte transaction
16 High bit rates or stronger pull-ups may require GPIOs to be set as High Drive, see GPIO chapter for more details.