DIEPEMPMSK

Address offset: 0x834

Device IN Endpoint FIFO Empty Interrupt Mask Register

This register is valid only in Dedicated FIFO operation (OTG_EN_DED_TX_FIFO = 1). This register is used to control the IN endpoint FIFO empty interrupt generation (DIEPINTn.TxfEmp).


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	INEPTXFEMPMSK										IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk) These bits acts as mask bits for DIEPINTn.TxFEmp interrupt, one bit per IN Endpoint: Bit 0 for IN EP 0, bit 15 for IN EP 15
			EP0MASK	1								Mask IN EP0 Tx FIFO Empty Interrupt
			EP1MASK	2								Mask IN EP1 Tx FIFO Empty Interrupt
			EP2MASK	4								Mask IN EP2 Tx FIFO Empty Interrupt
			EP3MASK	8								Mask IN EP3 Tx FIFO Empty Interrupt
			EP4MASK	16								Mask IN EP4 Tx FIFO Empty Interrupt
			EP5MASK	32								Mask IN EP5 Tx FIFO Empty Interrupt
			EP6MASK	64								Mask IN EP6 Tx FIFO Empty Interrupt
			EP7MASK	128								Mask IN EP7 Tx FIFO Empty Interrupt
			EP8MASK	256								Mask IN EP8 Tx FIFO Empty Interrupt
			EP9MASK	512								Mask IN EP9 Tx FIFO Empty Interrupt
			EP10MASK	1024								Mask IN EP10 Tx FIFO Empty Interrupt
			EP11MASK	2048								Mask IN EP11 Tx FIFO Empty Interrupt
			EP12MASK	4096								Mask IN EP12 Tx FIFO Empty Interrupt
			EP13MASK	8192								Mask IN EP13 Tx FIFO Empty Interrupt
			EP14MASK	16384								Mask IN EP14 Tx FIFO Empty Interrupt
			EP15MASK	32768								Mask IN EP15 Tx FIFO Empty Interrupt