To configure pins for SPIM use, see the corresponding PSEL.n registers.
The contents of registers PSEL.SCK, PSEL.CSN, PSEL.DCX, PSEL.MOSI, and PSEL.MISO are only used when SPIM is enabled, and retained while the device is in System ON mode. The PSEL.n registers can be configured only when SPIM is disabled in register ENABLE.
To ensure correct behavior, the pins used by SPIM must be configured in the GPIO peripheral as described in GPIO configuration before SPIM is enabled.
Only one peripheral can be assigned to drive a GPIO pin at a time. If more than one peripheral is assigned to a GPIO pin, it could result in unpredictable behavior.
| SPIM signal | SPIM pin | Direction | Output value |
|---|---|---|---|
| SCK | As specified in PSEL.SCK | Output | Same as CONFIG.CPOL |
| CSN | As specified in PSEL.CSN | Output | Same as CONFIG.CPOL |
| DCX | As specified in PSEL.DCX | Output | 1 |
| SDO | As specified in PSEL.MOSI | Output | 0 |
| SDI | As specified in PSEL.MISO | Input | Not applicable |
SPIM supports SPI modes [0..3]. The clock polarity (CPOL) and the clock phase (CPHA) are configured in register CONFIG.
| Mode | Clock polarity (CPOL) | Clock phase (CPHA) |
|---|---|---|
| SPI_MODE0 | 0 (Active High) | 0 (Leading) |
| SPI_MODE1 | 0 (Active High) | 1 (Trailing) |
| SPI_MODE2 | 1 (Active Low) | 0 (Leading) |
| SPI_MODE3 | 1 (Active Low) | 1 (Trailing) |