TIMER modes

TIMER can operate in two modes: Timer mode and Counter mode. In both modes, TIMER is started by triggering the START task, and stopped by triggering the STOP task. After TIMER stops, it can resume timing/counting by triggering the START task again. When timing/counting resumes, TIMER continues from the value it was on prior to stopping.

In Timer mode, TIMER's internal COUNTER register is incremented by one for every tick of the timer frequency f_TIMER, as shown in the following figure. The timer frequency is derived from PCLK as shown in the following example, using the values specified in the PRESCALER register.

    fTIMER = PCLK / (2PRESCALER)
  

For timers using PCLK16M as PCLK, when f_TIMER ≤ 1 MHz, TIMER uses PCLK1M instead of PCLK for reduced power consumption. Clock source selection between PCLK and PCLK1M is automatic according to the TIMER base frequency set by the prescaler.

In Counter mode, the TIMER's internal COUNTER register is incremented by one each time the COUNT task is triggered, meaning the timer frequency and the prescaler are not used in Counter mode. Similarly, the COUNT task has no effect in Timer mode.

The maximum value of TIMER is configured by changing the bit-width of the timer in register BITMODE.

PRESCALER and BITMODE must only be updated when TIMER is stopped. If these registers are updated while TIMER is started, unpredictable behavior may occur.

When TIMER is incremented beyond its maximum value, the Counter register will overflow and TIMER will automatically start over from zero.

The Counter register can be cleared by triggering the CLEAR task. This will explicitly set the internal value to zero.

TIMER implements multiple capture/compare registers.

Independent of prescaler settings, the accuracy of TIMER is equivalent to one tick of the timer frequency f_TIMER as shown in Timer/counter operation.