VPRSTATUS

Address offset: 0x804

VPR state information.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																														C	B	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	CPUSTATUS										Enumerates one of several possible states for the VPR:
			WAITING	0x0								WAITING (not yet started)
			RUNNING	0x1								RUNNING
			SLEEPING	0x2								SLEEPING
			INTERRUPT	0x3								INTERRUPT (in handler)
			EXCEPTION_TRAP	0x4								EXCEPTION/TRAP (in handler)
			ONGOING_RESET	0x5								ONGOING_RESET
			HALTED	0x6								HALTED
			ERROR	0xE								ERROR (lockup, needs debugging or reset)
B	R	RTPENABLED										Mirrors the ENABLERTPERIPH bit in the NORDIC.VPRNORDICCTRL CSR When this bit is cleared, it will override the APB read value of the INTEN register to 0.
			Disabled	0								Real-time peripherals disabled
			Enabled	1								Real-time peripherals enabled
C	R	RTPSTALL										Stalled waiting for real-time peripheral blocking CSR access, for example WAIT, OUTB with dirty status
			NotStalled	0								CPU not stalled on blocing CSR access.
			Stalled	1								CPU stalled on blocing CSR access.