DPPI latencies

DPPI task and event latency depends on the power domain of the source and destination peripherals.

DPPI signals operate on the HCLKCORE, PCLK32M, and PCLK16M clocks.

Table 1. DPPI clock frequency
Power domain	Clock source
MCU	HCLKCORE (64 or 128 MHz)
RADIO	PCLK32M (32 MHz)
PERI	PCLK16M (16 MHz)
LP	PCLK16M (16 MHz)

For peripherals in the same power domain, there is a two cycle delay from when an event is generated until a task subscribing to the same channel is triggered. Events that are generated while the system is sleeping will have additional access latency, as the system needs to request and provide sufficient resources for PPI handling. Examples of such events are the following:

A GPIO toggling and generating an event through GPIOTE
Events generated by GRTC while all other clocks are stopped

To improve PPI latency, the Constant Latency mode can be used, see Sub-power modes.

For peripherals in different power domains, additional access latency will apply. Events that are generated while the generating or receiving power domains are sleeping will have additional access latency, as the system needs to request and provide sufficient resources for PPI handling.