INTENSET00

Address offset: 0x488

Enable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID												W	V	U	T	S	R	Q	P	O	N		M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1S	READY										Write '1' to enable interrupt for event READY
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW W1S	TXREADY										Write '1' to enable interrupt for event TXREADY
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
C	RW W1S	RXREADY										Write '1' to enable interrupt for event RXREADY
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
D	RW W1S	ADDRESS										Write '1' to enable interrupt for event ADDRESS
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
E	RW W1S	FRAMESTART										Write '1' to enable interrupt for event FRAMESTART
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
F	RW W1S	PAYLOAD										Write '1' to enable interrupt for event PAYLOAD
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
G	RW W1S	END										Write '1' to enable interrupt for event END In TX: Last byte to be transmitted has been fetched from RAM In RX: Last byte received on air has been stored to RAM
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
H	RW W1S	PHYEND										Write '1' to enable interrupt for event PHYEND
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
I	RW W1S	DISABLED										Write '1' to enable interrupt for event DISABLED
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
J	RW W1S	DEVMATCH										Write '1' to enable interrupt for event DEVMATCH
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
K	RW W1S	DEVMISS										Write '1' to enable interrupt for event DEVMISS
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
L	RW W1S	CRCOK										Write '1' to enable interrupt for event CRCOK
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
M	RW W1S	CRCERROR										Write '1' to enable interrupt for event CRCERROR
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
N	RW W1S	BCMATCH										Write '1' to enable interrupt for event BCMATCH Bit counter value is specified in the RADIO.BCC register
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
O	RW W1S	EDEND										Write '1' to enable interrupt for event EDEND
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
P	RW W1S	EDSTOPPED										Write '1' to enable interrupt for event EDSTOPPED
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
Q	RW W1S	CCAIDLE										Write '1' to enable interrupt for event CCAIDLE
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
R	RW W1S	CCABUSY										Write '1' to enable interrupt for event CCABUSY
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
S	RW W1S	CCASTOPPED										Write '1' to enable interrupt for event CCASTOPPED
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
T	RW W1S	RATEBOOST										Write '1' to enable interrupt for event RATEBOOST
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
U	RW W1S	MHRMATCH										Write '1' to enable interrupt for event MHRMATCH
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
V	RW W1S	SYNC										Write '1' to enable interrupt for event SYNC For MODE=Ieee802154_250Kbit: A possible preamble has been received. However, due to the sporadic reception of noise, this event can be falsely triggered. For MODE=Ble_LR125Kbit, Ble_LR500Kbit: A possible preamble has been received. However, due to the sporadic reception of noise, this event can be falsely triggered. For MODE=Nrf_1Mbit, Nrf_2Mbit, Ble_1Mbit, or Ble_2Mbit: A possible preamble and the first two bytes of the address field has been received. The event can be generated falsely also in this mode. It is also possible that the event is not generated, or not generated before the ADDRESS event.
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
W	RW W1S	CTEPRESENT										Write '1' to enable interrupt for event CTEPRESENT
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled