Address offset: 0x7C9
Cache configuration
Configures the cache region size and line size
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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| ID | B | A | A | A | A | ||||||||||||||||||||||||||||||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A |
RW |
CACHESIZE |
0..15 |
Cache size is 2^CACHESIZE or (1 << CACHESIZE) KB, with a maximum size of 32KB (CACHESIZE = 5) To prevent RAM corruption or undefined behavior this field should only be modified when the cache is disabled |
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| B |
RW |
CACHELINESIZE |
Cache line size To prevent RAM corruption or undefined behavior this field should only be modified when the cache is disabled |
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CachelineSize32B |
0 |
Cache line size is 32 bytes (4 data units) |
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CachelineSize64B |
1 |
Cache line size is 64 bytes (8 data units) |
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