DEBUGIF.SBCS

Address offset: 0x4E0

System Bus Access Control and Status


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				N	N	N							M	L	K	J	J	J	I	H	G	G	G	F	F	F	F	F	F	F	E	D	C	B	A
Reset 0x20000000				0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	SBACCESS8										8-bit system bus accesses are supported.
B	R	SBACCESS16										16-bit system bus accesses are supported.
C	R	SBACCESS32										32-bit system bus accesses are supported.
D	R	SBACCESS64										64-bit system bus accesses are supported.
E	R	SBACCESS128										128-bit system bus accesses are supported.
F	R	SBASIZE										Width of system bus addresses in bits. (0 indicates there is no bus access support.)
G	R	SBERROR										When the Debug Module’s system bus master encounters an error, this field gets set. The bits in this field remain set until they are cleared by writing 1 to them. While this field is non-zero, no more system bus accesses can be initiated by the Debug Module. An implementation may report Other error (7) for any error condition.
			Normal	0								There was no bus error.
			Timeout	1								There was a timeout.
			Address	2								A bad address was accessed.
			Alignment	3								There was an alignment error.
			Size	4								An access of unsupported size was requested.
			Other	7								Other.
H	R	SBREADONDATA
			sbreadondata	1								Every read from sbdata0 automatically triggers a system bus read at the (possibly autoincremented) address.
I	R	SBAUTOINCREMENT
			sbautoincrement	1								sbaddress is incremented by the access size (in bytes) selected in sbaccess after every system bus access.
J	R	SBACCESS										Select the access size to use for system bus accesses. If sbaccess has an unsupported value when the DM starts a bus access, the access is not performed and sberror is set to 4.
			size8	0								8-bit.
			size16	1								16-bit.
			size32	2								32-bit.
			size64	3								64-bit.
			size128	4								128-bit.
K	R	SBREADONADDR
			sbreadonaddr	1								Every write to sbaddress0 automatically triggers a system bus read at the new address.
L	R	SBBUSY										(Whether the system bus itself is busy is related, but not the same thing.) This bit goes high immediately when a read or write is requested for any reason, and does not go low until the access is fully completed. Writes to sbcs while sbbusy is high result in undefined behavior. A debugger must not write to sbcs until it reads sbbusy as 0.
			notbusy	0								System bus master is not busy.
			busy	1								System bus master is busy.
M	R	SBBUSYERROR										Set when the debugger attempts to read data while a read is in progress, or when the debugger initiates a new access while one is already in progress (while sbbusy is set). It remains set until it’s explicitly cleared by the debugger. While this field is set, no more system bus accesses can be initiated by the Debug Module.
			noerror	0								No error.
			error	1								Debugger access attempted while one in progress.
N	R	SBVERSION
			version0	0								The System Bus interface conforms to mainline drafts of thia RISC-V External Debug Support spec older than 1 January, 2018.
			version1	1								The System Bus interface conforms to RISC-V External Debug Support version 0.13.2. Other values are reserved for future versions.