HCFG

RW

FSLSPCLKSEL

FS/LS PHY Clock Select (FSLSPclkSel)

When the core is in FS Host mode When the core is in LS Host mode Notes: - When Core in FS mode, the internal and external clocks have the same frequency. - When Core in LS mode, -- If FSLSPclkSel = 2'b00: Internal and external clocks have the same frequency -- If FSLSPclkSel = 2'b10: Internal clock is the divided by eight version of external 48 MHz clock

RW

FSLSSUPP

FS- and LS-Only Support (FSLSSupp)

The application uses this bit to control the core's enumeration speed. Using this bit, the application can make the core enumerate as a FS host, even If the connected device supports HS traffic. Do not make changes to this field after initial programming.

RW

ENA32KHZS

Enable 32 KHz Suspend mode (Ena32KHzS)

This bit can be set only in FS PHY interface is selected. Else, this bit needs to be set to zero. When FS PHY interface is chosen and this bit is set, the core expects that the PHY clock during Suspend is switched from 48 MHz to 32 KHz.

RW

RESVALID

Resume Validation Period (ResValid)

This field is effective only when HCFG.Ena32KHzS is set. It controls the resume period when the core resumes from suspend. The core counts for 'ResValid' number of clock cycles to detect a valid resume when this is set.

RW

MODECHTIMEN

Mode Change Ready Timer Enable (ModeChTimEn)

This bit is used to enable/disable the Host core to wait 200 PHY clock cycles at the end of Resume to change the opmode signal to the PHY to 00 after Suspend or LPM.