GUSBCFG

RW

TOUTCAL

Mode: Host and Device. HS/FS Timeout Calibration (TOutCal)

The number of PHY clocks that the application programs in this field is added to the high-speed/full-speed interpacket timeout duration in the core to account for any additional delays introduced by the PHY. This can be required, because the delay introduced by the PHY in generating the linestate condition can vary from one PHY to another. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this field based on the speed of enumeration. The number of bit times added per PHY clock are as follows: High-speed operation: - One 30-MHz PHY clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times

RW

PHYIF

Mode: Host and Device. PHY Interface (PHYIf)

The application uses this bit to configure the core to support a UTMI+ PHY with an 8- or 16-bit interface. When a ULPI PHY is chosen, this must be Set to 8-bit mode. This bit is writable only If UTMI+ and ULPI were selected. Otherwise, this bit returns the value for the power-on interface selected during configuration.

R

ULPIUTMISEL

Mode: Host and Device. ULPI or UTMI+ Select (ULPI_UTMI_Sel)

The application uses this bit to select either a UTMI+ interface or ULPI Interface.

R

FSINTF

Mode: Host and Device. Full-Speed Serial Interface Select (FSIntf)

The application uses this bit to select either a unidirectional or bidirectional USB 1.1 full-speed serial transceiver interface. If a USB 1.1 Full-Speed Serial Transceiver interface was not selected, this bit is always 0, with Write Only access. If a USB 1.1 FS interface was selected, Then the application can Set this bit to select between the 3- and 6-pin interfaces, and access is Read and Write. Note: For supporting the new 4-pin bi-directional interface, you need to select 6-pin unidirectional FS serial mode, and add an external control to convert it to a 4-pin interface.

R

PHYSEL

PHYSel

Mode: Host and Device USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select (PHYSel) The application uses this bit to select either a high-speed UTMI+ or ULPI PHY, or a full-speed transceiver. If a USB 1.1 Full-Speed Serial Transceiver interface was not selected in, this bit is always 0, with Write Only access. If a high-speed PHY interface was not selected in, this bit is always 1, with Write Only access. If both interface types were selected (parameters have non-zero values), the application uses this bit to select which interface is active, and access is Read and Write.

RW

USBTRDTIM

Mode: Device only. USB Turnaround Time (USBTrdTim)

Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to the Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). This must be programmed to Note:Refer to Programming Guide Section "Choosing the Value of GUSBCFG.USBTrdTim" for the turnaround time calculation. During the AHB Clock Frequency selection, it is recommended to consider mis-sampling into account for USBTrdTim. USB turnaround time is critical for certification where long cables and 5-Hubs are used. If you need the AHB to run at less than 30 MHz (or less than 42MHz when operating in 16-bit UTMI mode in HS speed), and if USB turnaround time is not critical, these bits can be programmed to a larger value.

RW

PHYLPWRCLKSEL

PHY Low-Power Clock Select (PhyLPwrClkSel)

Mode: Host and Device Selects either 480-MHz or 48-MHz (low-power) PHY mode. In FS and LS modes, the PHY can usually operate on a 48-MHz clock to save power. In 480 MHz mode, the UTMI interface operates at either 60 or 30-MHz, depending upon whether 8- or 16-bit data width is selected. In 48-MHz mode, the UTMI interface operates at 48 MHz in FS mode and at either 48 or 6 MHz in LS mode (depending on the PHY vendor). This bit drives the utmi_fsls_low_power core output signal, and is valid only for UTMI+ PHYs.

RW

TERMSELDLPULSE

Mode: Device only. TermSel DLine Pulsing Selection (TermSelDLPulse)

This bit selects utmi_termselect to drive data line pulse during SRP.

R

ICUSBCAP

Mode: Host and Device. IC_USB-Capable (IC_USBCap)

The application uses this bit to control the core's IC_USB capabilities. This bit is writable only if OTG_ENABLE_IC_USB=1 and OTG_FSPHY_INTERFACE!=0. The reset value depends on the configuration parameter OTG_SELECT_IC_USB when OTG_ENABLE_IC_USB = 1. In all other cases, this bit is set to 1'b0 and the bit is read only.

RW

TXENDDELAY

Mode: Device only. Tx End Delay (TxEndDelay)

Setting this bit to 1'b1 enables the controller to follow the TxEndDelay timings as per UTMI+ specification 1.05 section 4.1.5 for opmode signal during remote wakeup. The default value of this field is 1'b1 and it is not recommended to program it to 1'b0. The option to set it to 1'b0 (Normal Mode) is present only for debug purpose.

RW

FORCEHSTMODE

Mode: Host and device. Force Host Mode (ForceHstMode)

Writing a 1 to this bit forces the core to host mode irrespective of utmiotg_iddig input pin. After setting the force bit, the application must wait at least 25 ms before the change to take effect. When the simulation is in scale down mode, waiting for 500 micro sec is sufficient. This bit is valid only when OTG_MODE = 0, 1 or 2. In all other cases, this bit reads 0.

RW

FORCEDEVMODE

Mode:Host and device. Force Device Mode (ForceDevMode)

Writing a 1 to this bit forces the controller to device mode irrespective of utmiotg_iddig input pin. After setting the force bit, the application must wait at least 25 ms before the change to take effect. When the simulation is in scale down mode, waiting for 500 micro sec is sufficient. This bit is valid only when OTG_MODE = 0, 1 or 2. In all other cases, this bit reads 0.

W

CORRUPTTXPKT

Mode: Host and device. Corrupt Tx packet (CorruptTxPkt)

This bit is for debug purposes only. Never Set this bit to 1. The application must always write 1'b0 to this bit.