GOTGCTL

nRF54LM20A | nRF54LM20B Datasheet

Address offset: 0x000

Control and Status Register

The OTG Control and Status register controls the behavior and reflects the status of the OTG function of the controller.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID P O N N N N N M L K J I H G F E D C B A
Reset 0x000D0000 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

VBVALIDOVEN

Mode: Host only. VBUS Valid Override Enable (VbvalidOvEn)

This bit is used to enable/disable the software to override the Bvalid signal using the GOTGCTL.VbvalidOvVal.

DISABLED

0

Override is disabled and bvalid signal from the respective PHY selected is used internally by the controller

ENABLED

1

The vbus-valid signal received from the PHY is overridden with GOTGCTL.VbvalidOvVal

B

RW

VBVALIDOVVAL

Mode: Host only. VBUS Valid OverrideValue (VbvalidOvVal)

This bit is used to set Override value for vbusvalid signal when GOTGCTL.VbvalidOvEn is set.

SET0

0

vbusvalid value when GOTGCTL.VbvalidOvEn = 1

SET1

1

vbusvalid value when GOTGCTL.VbvalidOvEn is 1

C

RW

AVALIDOVEN

Mode: Host only. A-Peripheral Session Valid Override Enable (AvalidOvEn)

This bit is used to enable/disable the software to override the Avalid signal using the GOTGCTL.AvalidOvVal.

DISABLED

0

Derive AValid from PHY

ENABLED

1

Derive Avalid from GOTGCTL.AvalidOvVal

D

RW

AVALIDOVVAL

Mode: Host only. A-Peripheral Session Valid OverrideValue (AvalidOvVal)

This bit is used to set Override value for Avalid signal when GOTGCTL.AvalidOvEn is set.

VALUE0

0

Avalid value is 1'b0 when GOTGCTL.AvalidOvEn =1

VALUE1

1

Avalid value is 1'b1 when GOTGCTL.AvalidOvEn =1

E

RW

BVALIDOVEN

Mode: Device only. B-Peripheral Session Valid Override Value (BvalidOvEn)

This bit is used to enable/disable the software to override the Bvalid signal using the GOTGCTL.BvalidOvVal.

DISABLED

0

Override is disabled and bvalid signal from the respective PHY selected is used internally by the core

ENABLED

1

Internally Bvalid received from the PHY is overridden with GOTGCTL.BvalidOvVal

F

RW

BVALIDOVVAL

Mode: Device only. B-Peripheral Session Valid OverrideValue (BvalidOvVal)

This bit is used to set Override value for Bvalid signal when GOTGCTL.BvalidOvEn is set.

VALUE0

0

Bvalid value when GOTGCTL.BvalidOvEn =1

VALUE1

1

Bvalid value when GOTGCTL.BvalidOvEn =1

G

RW

DBNCEFLTRBYPASS

Mode: Host and Device. Debounce Filter Bypass

Bypass Debounce filters for avalid, bvalid, vbusvalid, sessend, iddig signals when enabled. Note: This register bit is valid only when debounce filters are present in core.

DISABLED

0

Debounce Filter Bypass is disabled.

ENABLED

1

Debounce Filter Bypass is enabled.

H

R

CONIDSTS

Mode: Host and Device. Connector ID Status (ConIDSts)

Indicates the connector ID status on a connect event. Note: The reset value of this register field can be read only after the PHY clock is stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to read the correct reset value which ever event is later. Reset: - 1'b0: in host only mode (OTG_MODE = 5 or 6) - 1'b1: in all other configurations

MODEA

0

The core is in A-Device mode.

MODEB

1

The core is in B-Device mode.

I

R

DBNCTIME

Mode: Host only. Long/Short Debounce Time (DbncTime)

Indicates the debounce time of a detected connection.

LONG

0

Long debounce time, used for physical connections (100 ms + 2.5 micro-sec)

SHORT

1

Short debounce time, used for soft connections (2.5 micro-sec)

J

R

ASESVLD

Mode: Host only. A-Session Valid (ASesVld)

Indicates the Host mode transceiver status. Note: If you do not enabled OTG features (such as SRP and HNP), the read reset value will be 1. The vbus assigns the values internally for non-SRP or non-HNP configurations. In case of OTG_MODE=0, the reset value of this bit is 1'b0.

NOTVALID

0

A-session is not valid.

VALID

1

A-session is valid.

K

R

BSESVLD

Mode: Device only. B-Session Valid (BSesVld)

Indicates the Device mode transceiver status. In OTG mode, you can use this bit to determine if the device is connected or disconnected. Note: - If you do not enable OTG features (such as SRP and HNP), the read reset value will be 1.The vbus assigns the values internally for non- SRP or non-HNP configurations. - In case of OTG_MODE=0, the reset value of this bit is 1'b0. - The reset value of this register field can be read only after the PHY clock is stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to read the correct reset value which ever event is later.

NOTVALID

0

B-session is not valid.

VALID

1

B-session is valid.

L

RW

OTGVER

OTG Version (OTGVer)

Indicates the OTG revision.

VER13

0

Supports OTG Version 1.3

VER20

1

Supports OTG Version 2.0

M

R

CURMOD

Current Mode of Operation (CurMod)

Mode: Host and Device Indicates the current mode. Reset: Note: The reset value of this register field can be read only after the PHY clock is stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to read the correct reset value which ever event is later.

DEVICEMODE

0

Current mode is device mode.

HOSTMODE

1

Current mode is host mode.

N

R

MULTVALIDBC

Mode: Host and Device. Multi Valued ID pin (MultValIdBC)

Battery Charger ACA inputs in the following order:

RIDC

1

B-Device connected to ACA. VBUS is on.

RIDB

2

B-Device connected to ACA. VBUS is off.

RIDA

4

A-Device connected to ACA

RIDGND

8

A-Device not connected to ACA

RIDFLOAT

16

B-Device not connected to ACA

O

RW

CHIRPEN

Mode: Device Only. This bit when programmed to 1'b1 results in the core asserting chirp_on before sending an actual Chirp "K" signal on USB. This bit is present only if OTG_BC_SUPPORT = 1.If OTG_BC_SUPPORT!=1, this bit is a reserved bit. Do not set this bit when core is operating in HSIC mode because HSIC always operates at High Speed and High speed chirp is not used

CHIRPDISABLE

0

The controller does not assert chirp_on before sending an actual Chirp "K" signal on USB.

CHIRPENABLE

1

The controller asserts chirp_on before sending an actual Chirp "K" signal on USB.

P

RW

EUSB2PHYDISCSUPP

This field is only applicable to Device mode and must be set to 1'b1 if eUSB2 PHY is used.

DISABLED

0

Device disconnect detection using GINTSTS.USBRst interrupt when not in hibernation and GPWRDN.ResetDetected when in hibernation

ENABLED

1

Device disconnect detection using GOTGINT.SesEEndDet interrupt when not in hibernation and GPWRDN.StsChngInt when in hibernation