GAHBCFG

RW

GLBLINTRMSK

Mode: Host and device. Global Interrupt Mask (GlblIntrMsk)

The application uses this bit to mask or unmask the interrupt line assertion to itself. Irrespective of this bit's setting, the interrupt status registers are updated by the controller.

RW

HBSTLEN

Mode: Host and device. Burst Length/Type (HBstLen)

This field is used in both External and Internal DMA modes. In External DMA mode, these bits appear on dma_burst[3:0] ports, which can be used by an external wrapper to interface the External DMA Controller interface to Synopsys DW_ahb_dmac or ARM PrimeCell. External DMA Mode defines the DMA burst length in terms of 32-bit words: Internal DMA Mode AHB Requester burst type:

RW

DMAEN

Mode: Host and device. DMA Enable (DMAEn)

This bit is always 0 when Completer-Only mode has been selected.

RW

NPTXFEMPLVL

Mode: Host and device. Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)

This bit is used only in Completer mode. In host mode and with Shared FIFO with device mode, this bit indicates when the Non-Periodic TxFIFO Empty Interrupt bit in the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered. With dedicated FIFO in device mode, this bit indicates when IN endpoint Transmit FIFO empty interrupt (DIEPINTn.TxFEmp) is triggered. Host mode and with Shared FIFO with device mode: Dedicated FIFO in device mode:

RW

PTXFEMPLVL

Mode: Host only. Periodic TxFIFO Empty Level (PTxFEmpLvl)

Indicates when the Periodic TxFIFO Empty Interrupt bit in the Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This bit is used only in Completer mode.

RW

REMMEMSUPP

Mode: Host and Device. Remote Memory Support (RemMemSupp)

This bit is programmed to enable the functionality to wait for the system DMA Done Signal for the DMA Write Transfers. - GAHBCFG.RemMemSupp=1 The int_dma_req output signal is asserted when the DMA starts write transfer to the external memory. When the core is done with the Transfers it asserts int_dma_done signal to flag the completion of DMA writes from the controller. The core then waits for sys_dma_done signal from the system to proceed further and complete the Data Transfer corresponding to a particular Channel/Endpoint. - GAHBCFG.RemMemSupp=0 The int_dma_req and int_dma_done signals are not asserted and the core proceeds with the assertion of the XferComp interrupt as soon as the DMA write transfer is done at the Core Boundary and it does not wait for the sys_dma_done signal to complete the DATA transfers.

RW

NOTIALLDMAWRIT

Mode: Host and Device. Notify All DMA Write Transactions (NotiAllDmaWrit)

This bit is programmed to enable the System DMA Done functionality for all the DMA write Transactions corresponding to the Channel/Endpoint. This bit is valid only when GAHBCFG.RemMemSupp is set to 1. - GAHBCFG.NotiAllDmaWrit = 1 The core asserts int_dma_req for all the DMA write transactions on the AHB interface along with int_dma_done, chep_last_transact and chep_number signal informations. The core waits for sys_dma_done signal for all the DMA write transactions in order to complete the transfer of a particular Channel/Endpoint. - GAHBCFG.NotiAllDmaWrit = 0 The core asserts int_dma_req signal only for the last transaction of DMA write transfer corresponding to a particular Channel/Endpoint. Similarly, the core waits for sys_dma_done signal only for that transaction of DMA write to complete the transfer of a particular Channel/Endpoint.

RW

AHBSINGLE

Mode: Host and Device. AHB Single Support (AHBSingle)

This bit when programmed supports Single transfers for the remaining data in a transfer when the core is operating in DMA mode. Note: If this feature is enabled, the AHB RETRY and SPLIT transfers still have INCR burst type. Enable this feature when the AHB Completer connected to the core does not support INCR burst (and when Split, and Retry transactions are not being used in the bus).

RW

LOAEOPCHECKCLKSBYTE

Mode: Host. Number of clock cycles to check for EOP SE0 for LOA logic

Note: - This field only affects USB2.0 FS operation in UTMI 8bit mode. The mac_prt logic checks for the programmed number of clocks of SE0 to validate an EOP for a packet. - The actual number of clocks checked will be the value programmed plus 1. So a value 1 results in checking for 2 clocks of SE0. Value of 3 checks 4 clocks of SE0 and so on. - The default value is 1, which results in 2 clocks of SE0 check.

RW

LOAEOPCHECKCLKSWORD

Mode: Host. Number of clock cycles to check for EOP SE0 for LOA logic

Note: - This field only affects USB2.0 FS operation in UTMI 16bit mode. The mac_prt logic checks for the programmed number of clocks of SE0 to validate an EOP for a packet. - The actual number of clocks checked will be the value programmed plus 1. So a value 1 results in checking for 2 clocks of SE0. Value of 3 checks 4 clocks of SE0 and so on. - The default value is 1, which results in 2 clocks of SE0 check.