DIEPMSK

Address offset: 0x810

Device IN Endpoint Common Interrupt Mask Register

This register works with each of the Device IN Endpoint Interrupt (DIEPINTn) registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTn register can be masked by writing to the corresponding bit in this register. Status bits are masked by default.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																						I					H		G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	XFERCOMPLMSK										Transfer Completed Interrupt Mask (XferComplMsk)
			MASK	0								Mask Transfer Completed Interrupt
			NOMASK	1								No Transfer Completed Interrupt Mask
B	RW	EPDISBLDMSK										Endpoint Disabled Interrupt Mask (EPDisbldMsk)
			MASK	0								Mask Endpoint Disabled Interrupt
			NOMASK	1								No Endpoint Disabled Interrupt Mask
C	RW	AHBERRMSK										AHB Error Mask (AHBErrMsk)
			MASK	0								Mask AHB Error Interrupt
			NOMASK	1								No AHB Error Interrupt Mask
D	RW	TIMEOUTMSK										Timeout Condition Mask (TimeOUTMsk) (Non-isochronous endpoints)
			MASK	0								Mask Timeout Condition Interrupt
			NOMASK	1								No Timeout Condition Interrupt Mask
E	RW	INTKNTXFEMPMSK										IN Token Received When TxFIFO Empty Mask (INTknTXFEmpMsk)
			MASK	0								Mask IN Token Received When TxFIFO Empty Interrupt
			NOMASK	1								No IN Token Received When TxFIFO Empty Interrupt
F	RW	INTKNEPMISMSK										IN Token received with EP Mismatch Mask (INTknEPMisMsk)
			MASK	0								Mask IN Token received with EP Mismatch Interrupt
			NOMASK	1								No Mask IN Token received with EP Mismatch Interrupt
G	RW	INEPNAKEFFMSK										IN Endpoint NAK Effective Mask (INEPNakEffMsk)
			MASK	0								Mask IN Endpoint NAK Effective Interrupt
			NOMASK	1								No IN Endpoint NAK Effective Interrupt Mask
H	RW	TXFIFOUNDRNMSK										Fifo Underrun Mask (TxfifoUndrnMsk)
			MASK	0								Mask Fifo Underrun Interrupt
			NOMASK	1								No Fifo Underrun Interrupt Mask
I	RW	NAKMSK										NAK interrupt Mask (NAKMsk)
			MASK	0								Mask NAK Interrupt
			NOMASK	1								No Mask NAK Interrupt