Address offset: 0x804
Device Control Register
This register is used to control the characteristics of the Device controller.
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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| ID | O | N | M | L | K | J | I | H | G | F | E | E | E | D | C | B | A | ||||||||||||||||||
| Reset 0x00000002 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A |
RW |
RMTWKUPSIG |
Remote Wakeup Signaling (RmtWkUpSig) When the application sets this bit, the core initiates remote signaling to wake up the USB host. The application must Set this bit to instruct the core to exit the Suspend state. As specified in the USB 2.0 specification, the application must clear this bit 1-15 ms after setting it. If LPM is enabled and the core is in the L1 (Sleep) state, when the application sets this bit, the core initiates L1 remote signaling to wake up the USB host. The application must set this bit to instruct the core to exit the Sleep state. As specified in the LPM specification, the hardware automatically clears this bit 50 microseconds (TL1DevDrvResume) after being set by the application. The application must not set this bit when GLPMCFG bRemoteWake from the previous LPM transaction is zero. |
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DISABLEDRMWKUP |
0 |
Core does not send Remote Wakeup Signaling |
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ENABLERMWKUP |
1 |
Core sends Remote Wakeup Signaling |
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| B |
RW |
SFTDISCON |
Soft Disconnect (SftDiscon) The application uses this bit to signal the controller to do a soft disconnect. As long as this bit is set, the host does not see that the device is connected, and the device does not receive signals on the USB. The core stays in the disconnected state until the application clears this bit. UTMI+ to 2'b00, which generates a device connect event to the USB host. When the device is reconnected, the USB host restarts device enumeration. The following is the minimum duration under various conditions for which this bit must be set for the USB host to detect a device disconnect. To accommodate clock jitter, it is recommended that the application adds some extra delay to the specified minimum duration. For high speed, if the device state is, - Suspended, the minimum duration is 1ms + 2.5us - Idle, the minimum duration is 3ms + 2.5us - Not Idle or Suspended (performing transactions), the minimum duration 125 us For full speed/low speed, if the device state is, - Suspended, the minimum duration is 1ms + 2.5us - Idle, the minimum duration is 2.5us - Not Idle or Suspended (performing transactions), the minimum duration 125 us Note: - This bit can be also used for ULPI/FS Serial interfaces. - This bit is not impacted by a soft reset. |
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NODISCONNECT |
0 |
The core drives the phy_opmode_o signal on the UTMI+ to 2'b00, which generates a device connect event to the USB host |
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DISCONNECT |
1 |
The core drives the phy_opmode_o signal on the UTMI+ to 2'b01, which generates a device disconnect event to the USB host |
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| C |
R |
GNPINNAKSTS |
Global Non-periodic IN NAK Status (GNPINNakSts) - 1'b0: A handshake is sent out based on the data availability in the transmit FIFO. |
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INACTIVE |
0 |
A handshake is sent out based on the data availability in the transmit FIFO |
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ACTIVE |
1 |
A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO. |
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| D |
R |
GOUTNAKSTS |
Global OUT NAK Status (GOUTNakSts) - 1'b0: A handshake is sent based on the FIFO Status and the NAK and STALL bit settings. |
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INACTIVE |
0 |
A handshake is sent based on the FIFO Status and the NAK and STALL bit settings. |
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ACTIVE |
1 |
No data is written to the RxFIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT packets are dropped. |
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| E |
RW |
TSTCTL |
Test Control (TstCtl) - 3'b000: Test mode disabled |
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DISABLED |
0 |
Test mode disabled |
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TESTJ |
1 |
Test_J mode |
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TESTK |
2 |
Test_K mode |
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TESTSN |
3 |
Test_SE0_NAK mode |
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TESTPM |
4 |
Test_Packet mode |
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TESTFE |
5 |
Test_force_Enable |
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| F |
W |
SGNPINNAK |
Set Global Non-periodic IN NAK (SGNPInNak) A write to this field sets the Global Non-periodic IN NAK.The application uses this bit to send a NAK handshake on all non-periodic IN endpoints. The core can also Set this bit when a timeout condition is detected on a non-periodic endpoint in shared FIFO operation. The application must Set this bit only after making sure that the Global IN NAK Effective bit in the Core Interrupt Register (GINTSTS.GINNakEff) is cleared |
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DISABLE |
0 |
Disable Global Non-periodic IN NAK |
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ENABLE |
1 |
Set Global Non-periodic IN NAK |
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| G |
W |
CGNPINNAK |
Clear Global Non-periodic IN NAK (CGNPInNak) A write to this field clears the Global Non-periodic IN NAK. |
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DISABLE |
0 |
Disable Global Non-periodic IN NAK |
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ENABLE |
1 |
Clear Global Non-periodic IN NAK |
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| H |
W |
SGOUTNAK |
Set Global OUT NAK (SGOUTNak) A write to this field sets the Global OUT NAK. The application uses this bit to send a NAK handshake on all OUT endpoints. The application must set the this bit only after making sure that the Global OUT NAK Effective bit in the Core Interrupt Register (GINTSTS.GOUTNakEff) is cleared. |
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DISABLED |
0 |
Disable Global OUT NAK |
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ENABLED |
1 |
Set Global OUT NAK |
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| I |
W |
CGOUTNAK |
Clear Global OUT NAK (CGOUTNak) A write to this field clears the Global OUT NAK. |
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DISABLED |
0 |
Disable Clear Global OUT NAK |
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ENABLED |
1 |
Clear Global OUT NAK |
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| J |
RW |
PWRONPRGDONE |
Power-On Programming Done (PWROnPrgDone) The application uses this bit to indicate that register programming is completed after a wake-up from Power Down mode. |
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NOTDONE |
0 |
Power-On Programming not done |
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DONE |
1 |
Power-On Programming Done |
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| K |
RW |
IGNRFRMNUM |
Ignore Frame Number Feature for Isochronous Endpoints (IgnrFrmNum) This field is also used to control the Periodic Transfer Interrupt (PTI) feature. Note: Do not program IgnrFrmNum bit to 1'b1 when the core is operating in threshold mode. Completer Mode (GAHBCFG.DMAEn=0): This bit is not valid in Completer mode and must not be programmed to 1. Scatter/Gather DMA Mode (GAHBCFG.DMAEn=1,DCFG.DescDMA=1): Note: When Scatter/Gather DMA mode is enabled this feature is not applicable to High Speed, High bandwidth transfers. When this bit is enabled, there must be only one packet per descriptor. - 0: The core transmits the packets only in the frame number in which they are intended to be transmitted. - 1: The core ignores the frame number, sending packets immediately as the packets are ready. In Scatter/Gather DMA mode, if this bit is enabled, the packets are not flushed when a ISOC IN token is received for an elapsed frame. Non-Scatter/Gather DMA Mode, that is, Buffer DMA Mode (GAHBCFG.DMAEn=1,DCFG.DescDMA=0): When Scatter/Gather DMA mode is disabled, this field is used by the application to enable Periodic Transfer Interrupt (PTI) Mode. The application can program Periodic Endpoint transfers for multiple (micro)Frames. - 0: Periodic Transfer Interrupt feature is disabled, application needs to program transfers for periodic endpoints every (micro)Frame - 1: Periodic Transfer Interrupt feature is enabled, application can program transfers for multiple (micro)Frames for periodic endpoints. In the PTI mode, the application receives Transfer Complete Interrupt after transfers for multiple (micro)Frames are completed. |
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DISABLED |
0 |
Scatter/Gather DMA Mode: The core transmits the packets only in the frame number in which they are intended to be transmitted.Non-Scatter/Gather DMA Mode: Periodic Transfer Interrupt feature is disabled. |
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ENABLED |
1 |
Scatter/Gather DMA Mode: The core ignores the frame number, sending packets immediately as the packets are ready.Non-Scatter/Gather DMA Mode: Periodic Transfer Interrupt feature is enabled. |
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| L |
RW |
NAKONBBLE |
NAK on Babble Error (NakOnBble) Set NAK automatically on babble (NakOnBble). The core sets NAK automatically for the endpoint on which babble is received. |
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DISABLED |
0 |
Disable NAK on Babble Error |
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ENABLED |
1 |
NAK on Babble Error |
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| M |
RW |
DEEPSLEEPBESLREJECT |
DeepSleepBESLReject - 1: Deep Sleep BESL Reject feature is enabled - 0: Deep Sleep BESL Reject feature is disabled Core rejects LPM request with HIRD value greater than HIRD threshold programmed. NYET response is sent for LPM tokens with HIRD value greater than HIRD threshold. By default, the Deep Sleep BESL Reject feature is disabled. |
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DISABLED |
0 |
Deep Sleep BESL Reject feature is disabled |
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ENABLED |
1 |
Deep Sleep BESL Reject feature is enabled |
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| N |
RW |
SERVINT |
Service Interval based scheduling for Isochronous IN Endpoints This field is used to enable service interval based scheduling feature for ISOC IN EPs. Note: This bit is applicable only in device mode and when Scatter/Gather DMA mode is used. This feature must not be enabled along with DCTL.IgnrFrmNum. Scatter/Gather DMA Mode (GAHBCFG.DMAEn=1,DCFG.DescDMA=1): When this bit is enabled, the frame number field in the ISOC IN descriptor structure is interpreted as the last frame of the service interval. In Scatter/Gather DMA mode, if this bit is enabled, the pending packets are flushed by the controller at the last frame of the service interval. |
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DISABLED |
0 |
The controller behavior depends on DCTL.IgnrFrmNum field. |
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ENABLED |
1 |
Scatter/Gather DMA Mode: The controller can transmit the packets in any frame of the service interval. |
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| O |
RW |
UTMITERMSELCORRDIS |
Disable the correction of TermSel on UTMI Interface. When the application sets Soft disconnect (DCTL.SftDiscon=1'b1), the behavior of TermSel has been corrected to drive the valid combination of XcvrSel (FS_XCVR) and TermSel (FS_TERM). The application can set this register bit to 1'b1 to fall back to the original behavior of the Device controller driving XcvrSel (FS_XCVR) and TermSel (HS_TERM) when Soft disconnect is set (DCTL.SftDiscon=1'b1). Note: The application must program this register during Device Initialization before USB Reset and this value cannot be changed afterwards. |
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DISABLED |
0 |
Valid Combination of XcvrSel and TermSel is driven by the Device Controller. |
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ENABLED |
1 |
Invalid Combination of XcvrSel and TermSel is driven by the Device Controller. |
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