DCFG

RW

DEVSPD

Device Speed (DevSpd)

Indicates the speed at which the application requires the core to enumerate, or the maximum speed the application can support. However, the actual bus speed is determined only after the connect sequence is completed, and is based on the speed of the USB host to which the core is connected.

RW

NZSTSOUTHSHK

Non-Zero-Length Status OUT Handshake (NZStsOUTHShk)

The application can use this field to select the handshake the core sends on receiving a nonzero-length data packet during the OUT transaction of a control transfer's Status stage.

RW

ENA32KHZSUSP

Enable 32 KHz Suspend mode (Ena32KHzSusp)

This bit can be set only if FS PHY interface is selected. Otherwise, this bit needs to be set to zero. If FS PHY interface is chosen and this bit is set, the PHY clock during Suspend must be switched from 48 MHz to 32 KHz.

RW

DEVADDR

Device Address (DevAddr)

The application must program this field after every SetAddress control command.

RW

PERFRINT

Periodic Frame Interval (PerFrInt)

Indicates the time within a (micro)Frame at which the application must be notified using the End Of Periodic Frame Interrupt. This can be used to determine If all the isochronous traffic for that (micro)Frame is complete.

RW

XCVRDLY

XCVRDLY

Enables or disables delay between xcvr_sel and txvalid during device chirp

RW

ERRATICINTMSK

Erratic Error Interrupt Mask

RW

IPGISOCSUPT

Worst-Case Inter-Packet Gap ISOC OUT Support (ipgisocSupt)

This bit indicates that the controller supports the worst-case scenario of Rx followed by Rx Inter-Packet Gap (IPG) (32 bit times) as per the UTMI Specification for any token following an ISOC OUT token. Without this support, when any token follows an ISOC OUT token with the worst-case IPG, the controller does not detect the followed token. The worst-case IPG of the controller without this support depends on the AHB and PHY clock frequency.

RW

PERSCHINTVL

Periodic Scheduling Interval (PerSchIntvl)

PerSchIntvl must be programmed for Scatter/Gather DMA mode. This field specifies the amount of time the Internal DMA engine must allocate for fetching periodic IN endpoint data. Based on the number of periodic endpoints, this value must be specified as 25,50 or 75% of (micro)Frame. - When any periodic endpoints are active, the internal DMA engine allocates the specified amount of time in fetching periodic IN endpoint data . - When no periodic endpoints are active, Then the internal DMA engine services non-periodic endpoints, ignoring this field. - After the specified time within a (micro)Frame, the DMA switches to fetching for non-periodic endpoints.

RW

RESVALID

Resume Validation Period (ResValid)

This field is effective only when DCFG.Ena32KHzSusp is set. It controls the resume period when the core resumes from suspend. The core counts for ResValid number of clock cycles to detect a valid resume when this bit is set