PIN_CNF[n]

Address offset: 0x080 + (n × 0x4)

Pin n configuration of GPIO pin

This register is retained.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID					G	G	G											F	F					E	E	D	D					C	C	B	A
Reset 0x00000002				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0
ID	R/W	Field	Value ID	Value								Description
A	RW	DIR										Pin direction. Same physical register as DIR register
			Input	0								Configure pin as an input pin
			Output	1								Configure pin as an output pin
B	RW	INPUT										Connect or disconnect input buffer
			Connect	0								Connect input buffer
			Disconnect	1								Disconnect input buffer
C	RW	PULL										Pull configuration
			Disabled	0								No pull
			Pulldown	1								Pull-down on pin
			Pullup	3								Pull-up on pin
D	RW	DRIVE0										Drive configuration for '0'
			S0	0								Standard '0'
			H0	1								High drive '0'
			D0	2								Disconnect '0'(normally used for wired-or connections)
			E0	3								Extra high drive '0' Note: The DRIVE1 must be E1 as well to work properly.
E	RW	DRIVE1										Drive configuration for '1'
			S1	0								Standard '1'
			H1	1								High drive '1'
			D1	2								Disconnect '1'(normally used for wired-or connections)
			E1	3								Extra high drive '1' Note: The DRIVE0 must be E0 as well to work properly.
F	RW	SENSE										Pin sensing mechanism
			Disabled	0								Disabled
			High	2								Sense for high level
			Low	3								Sense for low level
G	RW	CTRLSEL										Select which module has direct control over this pin Note: this field is only accessible from secure code
			GPIO	0x0								GPIO or peripherals with PSEL registers
			VPR	0x1								VPR processor
			GRTC	0x4								GRTC peripheral