Address offset: 0x03C
Status
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | F | F | F | F | F | F | F | F | F | F | F | F | F | F | F | F | E | D | C | B | A | ||||||||||||||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A |
R |
FETCHBUSY |
This bit is high as long as the fetcher DMA is busy. |
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| B |
R |
PUSHBUSY |
This bit is high as long as the pusher DMA is busy. |
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| C |
R |
FETCHNOTEMPTY |
Not empty flag for fetcher DMA input FIFO |
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| D |
R |
PUSHWAITINGFIFO |
Pusher DMA Waiting FIFO. This bit is high when the pusher is waiting for more data in output FIFO. |
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| E |
R |
SOFTRSTBUSY |
This bit is high when the soft reset is on going |
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| F |
R |
PUSHNBDATA |
Amount of data in the pusher DMA output FIFO |
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