CONFIG.MCK.DIV

Address offset: 0x510

MCK divider.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	DIV										MCK frequency configuration Use either the provided enumerated values, or use the equation. NOTE: The 12 least significant bits of the register are ignored and shall be set to zero.
			CKDIV2	0x80000000								CK divided by 2
			CKDIV3	0x50000000								CK divided by 3
			CKDIV4	0x40000000								CK divided by 4
			CKDIV5	0x30000000								CK divided by 5
			CKDIV6	0x28000000								CK divided by 6
			CKDIV8	0x20000000								CK divided by 8
			CKDIV10	0x18000000								CK divided by 10
			CKDIV11	0x16000000								CK divided by 11
			CKDIV15	0x11000000								CK divided by 15
			CKDIV16	0x10000000								CK divided by 16
			CKDIV21	0x0C000000								CK divided by 21
			CKDIV23	0x0B000000								CK divided by 23
			CKDIV30	0x08800000								CK divided by 30
			CKDIV31	0x08400000								CK divided by 31
			CKDIV32	0x08000000								CK divided by 32
			CKDIV42	0x06000000								CK divided by 42
			CKDIV63	0x04100000								CK divided by 63
			CKDIV125	0x020C0000								CK divided by 125