GPWRDN

RW

PMUINTSEL

PMU Interrupt Select (PMUIntSel)

A write to this bit with 1'b1 enables the PMU to generate interrupts to the application. During this state all interrupts from the DWC_otg_core module are blocked to the application. Note: This bit must be set to 1'b1 before the core is put into hibernation. Note: This bit must not be written to during normal mode of operation.

RW

PMUACTV

PMU Active (PMUActv)

This is bit is to enable or disable the PMU logic. Note: This bit must not be written to during normal mode of operation.

RW

RESTORE

Restore

The application must program this bit to enable or disable restore mode from the PMU module. Note: This bit must not be written to during normal mode of operation.

RW

PWRDNCLMP

Power Down Clamp (PwrDnClmp)

The application must program this bit to enable or disable the clamps to all the outputs of the core module to prevent the corruption of other active logic.

RW

PWRDNRSTN

Power Down ResetN (PwrDnRst_n)

The application must program this bit to reset the core during the Hibernation exit process or during ADP when powering up the core (in case the core was powered off during ADP process). Note: This bit must not be written to during normal mode of operation.

RW

PWRDNSWTCH

Power Down Switch (PwrDnSwtch)

This bit indicates to the controller whether the VDD switch is in ON/OFF state. Note: This bit must not be written to during normal mode of operation.

RW

DISABLEVBUS

DisableVBUS

Host Mode: The application must program this bit if HPRT0.PrtPwr was programmed to 0 before entering Hibernation. This is to indicate PMU whether session was ended before entering Hibernation. Device Mode: The application must program this bit to inform the PMU whether the bvalid valid signal is high (session valid) or low (session end) whenever the core is switched off. This bit is valid only when GPWRDN.PMUActv is 1.

RW

LNSTSCHNG

Line State Change (LnStsChng)

This interrupt is asserted when there is a Linestate Change detected by the PMU. The application must read GPWRDN.Linestate to determine the current linestate on USB. This bit is valid only when GPWRDN.PMUActv is 1.

RW

LINESTAGECHANGEMSK

LineStageChangeMsk

Mask for LineStateChange interrupt.

RW

RESETDETECTED

ResetDetected

This field indicates that Reset has been detected by the PMU module. This field generates an interrupt.

RW

RESETDETMSK

ResetDetMsk

Mask for ResetDetected interrupt

RW

DISCONNECTDETECT

DisconnectDetect

This field indicates that Disconnect has been detected by the PMU. This field generates an interrupt. After detecting disconnect during hibernation the application must not restore the core, but instead start the initialization process.

RW

DISCONNECTDETECTMSK

DisconnectDetectMsk

Mask For DisconnectDetect Interrupt

RW

CONNECTDET

ConnectDet

This field indicates that a new connect has been detected

RW

CONNDETMSK

ConnDetMsk

Mask for ConnectDet interrupt

RW

SRPDETECT

SRPDetect

This field indicates that SRP has been detected by the PMU. This field generates an interrupt. After detecting SRP during hibernation the application must not restore the core. The application must get into the initialization process.

RW

SRPDETECTMSK

SRPDetectMsk

Mask for SRPDetect Interrupt

RW

STSCHNGINT

Status Change Interrupt (StsChngInt)

This field indicates a status change in either the IDDIG or BSessVld signal. After receiving this interrupt the application must read the GPWRDN register and interpret the change in IDDIG or BSesVld with respect to the previous value stored by the application. Note: When Battery Charger is enabled and the ULPI interface is used, if StsChngInt is received and the application reads GPWRDN register and determines that it is because of a change in the value of IDDIG, then StsChngInt may be generated once again within the next few clock cycles. This occurs because of an ambiguity in the implementation of Battery Charger Support over the ULPI interface. After receiving the StsChngInt for the second time the application can once again read the GPWRDN register. However, this time the valueIDDIG (or BSesVld) would not have changed. The application then processes the second interrupt but no further action will be required as a result.

RW

STSCHNGINTMSK

StsChngIntMsk

Mask for StsChng Interrupt

R

LINESTATE

LineState

This field indicates the current linestate on USB as seen by the PMU module. This bit is valid only when GPWRDN.PMUActv is 1.

R

IDDIG

This bit indicates the status of the signal IDDIG. The application must read this bit after receiving GPWRDN.StsChngInt and decode based on the previous value stored by the application.

Indicates the current mode. This bit is valid only when GPWRDN.PMUActv is 1.

R

BSESSVLD

B Session Valid (BSessVld)

This field reflects the B session valid status signal from the PHY. This bit is valid only when GPWRDN.PMUActv is 1.

R

MULTVALIDBC

MultValIdBC

Battery Charger ACA inputs in the following order: These bits are present only if BC_SUPPORT = 1. Otherwise, these bits are reserved and will read 5'h0.