INTENSET

Address offset: 0x304

Enable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID														V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW W1S	STARTED										Write '1' to enable interrupt for event STARTED
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW W1S	END										Write '1' to enable interrupt for event END
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
C	RW W1S	DONE										Write '1' to enable interrupt for event DONE
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
D	RW W1S	RESULTDONE										Write '1' to enable interrupt for event RESULTDONE
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
E	RW W1S	CALIBRATEDONE										Write '1' to enable interrupt for event CALIBRATEDONE
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
F	RW W1S	STOPPED										Write '1' to enable interrupt for event STOPPED
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
G	RW W1S	CH0LIMITH										Write '1' to enable interrupt for event CH0LIMITH
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
H	RW W1S	CH0LIMITL										Write '1' to enable interrupt for event CH0LIMITL
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
I	RW W1S	CH1LIMITH										Write '1' to enable interrupt for event CH1LIMITH
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
J	RW W1S	CH1LIMITL										Write '1' to enable interrupt for event CH1LIMITL
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
K	RW W1S	CH2LIMITH										Write '1' to enable interrupt for event CH2LIMITH
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
L	RW W1S	CH2LIMITL										Write '1' to enable interrupt for event CH2LIMITL
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
M	RW W1S	CH3LIMITH										Write '1' to enable interrupt for event CH3LIMITH
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
N	RW W1S	CH3LIMITL										Write '1' to enable interrupt for event CH3LIMITL
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
O	RW W1S	CH4LIMITH										Write '1' to enable interrupt for event CH4LIMITH
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
P	RW W1S	CH4LIMITL										Write '1' to enable interrupt for event CH4LIMITL
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
Q	RW W1S	CH5LIMITH										Write '1' to enable interrupt for event CH5LIMITH
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
R	RW W1S	CH5LIMITL										Write '1' to enable interrupt for event CH5LIMITL
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
S	RW W1S	CH6LIMITH										Write '1' to enable interrupt for event CH6LIMITH
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
T	RW W1S	CH6LIMITL										Write '1' to enable interrupt for event CH6LIMITL
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
U	RW W1S	CH7LIMITH										Write '1' to enable interrupt for event CH7LIMITH
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
V	RW W1S	CH7LIMITL										Write '1' to enable interrupt for event CH7LIMITL
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled