DOEPCTL0

R

MPS

Maximum Packet Size (MPS)

The maximum packet size for control OUT endpoint 0 is the same as what is programmed in control IN Endpoint 0.

R

USBACTEP

USB Active Endpoint (USBActEP)

This bit is always set to 1, indicating that a control endpoint 0 is always active in all configurations and interfaces.

R

NAKSTS

NAK Status (NAKSts)

Indicates the following: When either the application or the core sets this bit, the core stops receiving data, even If there is space in the RxFIFO to accommodate the incoming packet. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

R

EPTYPE

Endpoint Type (EPType)

Hardcoded to 2'b00 for control.

RW

STALL

STALL Handshake (Stall)

The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit or Global OUT NAK is Set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

W

CNAK

Clear NAK (CNAK)

A write to this bit clears the NAK bit for the endpoint.

W

SNAK

Set NAK (SNAK)

A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also set bit on a Transfer Completed interrupt, or after a SETUP is received on the endpoint.

R

EPDIS

Endpoint Disable (EPDis)

The application cannot disable control OUT endpoint 0.

RW

EPENA

Endpoint Enable (EPEna)

- When Scatter/Gather DMA mode is enabled, for OUT endpoints this bit indicates that the descriptor structure and data buffer to receive data is setup. - When Scatter/Gather DMA mode is disabled (such as for buffer-pointer based DMA mode)this bit indicates that the application has allocated the memory to start receiving data from the USB. - The core clears this bit before setting any of the following interrupts on this endpoint: -- SETUP Phase Done -- Endpoint Disabled -- Transfer Completed Note: In DMA mode, this bit must be set for the core to transfer SETUP data packets into memory and it is not cleared on Transfer Completed interrupt of SETUP packet.