Address offset: 0xB10
Device OUT Endpoint 0 Transfer Size Register
This register contains the Transfer Size for the OUT Endpoint 0 of the Device controller.
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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| ID | C | C | B | A | A | A | A | A | A | A | |||||||||||||||||||||||||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A |
RW |
XFERSIZE |
Transfer Size (XferSize) Indicates the transfer size in bytes for endpoint 0. The core interrupts the application only after it has exhausted the transfer size amount of data. The transfer size can be Set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core decrements this field every time a packet is read from the RxFIFO and written to the external memory. |
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| B |
RW |
PKTCNT |
Packet Count (PktCnt) This field is decremented to zero after a packet is written into the RxFIFO. |
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| C |
RW |
SUPCNT |
SETUP Packet Count (SUPCnt) This field specifies the number of back-to-back SETUP data packets the endpoint can receive. |
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ONEPACKET |
1 |
1 packet |
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TWOPACKET |
2 |
2 packets |
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THREEPACKET |
3 |
3 packets |
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