Address offset: 0x510
Power configuration
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | B | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | ||||||||||||||||||
| Reset 0x00000100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A |
RW |
ACCESSTIMEOUT |
Access timeout, in 31.25 ns units, used for going into standby power mode or remain active on wake up The timeout counter counts down and is restarted on every RRAM access and on event WOKENUP |
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| B |
RW |
POF |
Power on failure warning handling configuration |
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|
Wait |
0 |
Wait until the current RRAM write finishes |
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|
Abort |
1 |
Abort the current RRAM write |
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