Address offset: 0x508 + (n × 0x18)
Host Channel Interrupt Register 0
This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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| ID | K | J | I | H | G | F | E | D | C | B | A | ||||||||||||||||||||||||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A |
RW |
XFERCOMPL |
Transfer Completed (XferCompl) Transfer completed normally without any errors.This bit can be set only by the core and the application must write 1 to clear it. - For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor. - In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors. |
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INACTIVE |
0 |
Transfer in progress or No Active Transfer |
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ACTIVE |
1 |
Transfer completed normally without any errors |
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| B |
RW |
CHHLTD |
Channel Halted (ChHltd) In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer. In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following - EOL being set in descriptor - AHB error - Excessive transaction errors - Babble - Stall |
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INACTIVE |
0 |
Channel not halted |
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ACTIVE |
1 |
Channel Halted |
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| C |
RW |
AHBERR |
AHB Error (AHBErr) This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address. For details, see "AHB Error Handling" in the Programming Guide. |
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INACTIVE |
0 |
No AHB error |
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ACTIVE |
1 |
AHB error during AHB read/write |
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| D |
RW |
STALL |
STALL Response Received Interrupt (STALL) In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application must write 1 to clear it. |
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INACTIVE |
0 |
No Stall Response Received Interrupt |
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ACTIVE |
1 |
Stall Response Received Interrupt |
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| E |
RW |
NAK |
NAK Response Received Interrupt (NAK) In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application must write 1 to clear it. |
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INACTIVE |
0 |
No NAK Response Received Interrupt |
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ACTIVE |
1 |
NAK Response Received Interrupt |
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| F |
RW |
ACK |
ACK Response Received/Transmitted Interrupt (ACK) In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application must write 1 to clear it. |
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INACTIVE |
0 |
No ACK Response Received or Transmitted Interrupt |
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ACTIVE |
1 |
ACK Response Received or Transmitted Interrup |
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| G |
RW |
NYET |
NYET Response Received Interrupt (NYET) In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application must write 1 to clear it. |
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INACTIVE |
0 |
No NYET Response Received Interrupt |
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ACTIVE |
1 |
NYET Response Received Interrupt |
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| H |
RW |
XACTERR |
Transaction Error (XactErr) Indicates one of the following errors occurred on the USB. - CRC check failure - Timeout - Bit stuff error - False EOP In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application must write 1 to clear it. |
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INACTIVE |
0 |
No Transaction Error |
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ACTIVE |
1 |
Transaction Error |
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| I |
RW |
BBLERR |
Babble Error (BblErr) In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application must write 1 to clear it. |
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INACTIVE |
0 |
No Babble Error |
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ACTIVE |
1 |
Babble Error |
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| J |
RW |
FRMOVRUN |
Frame Overrun (FrmOvrun). In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application must write 1 to clear it. |
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INACTIVE |
0 |
No Frame Overrun |
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ACTIVE |
1 |
Frame Overrun |
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| K |
RW |
DATATGLERR |
Data Toggle Error (DataTglErr).This bit can be set only by the core and the application must write 1 to clear it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. |
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INACTIVE |
0 |
No Data Toggle Error |
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ACTIVE |
1 |
Data Toggle Error |
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