Address offset: 0x05C
Global DFIFO Configuration Register
Register to configure the DFIFOs for the controller.
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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| ID | B | B | B | B | B | B | B | B | B | B | B | B | B | B | B | B | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
| Reset 0x0BE00C00 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A |
RW |
GDFIFOCFG |
GDFIFOCfg This field is for dynamic programming of the DFIFO Size. This value takes effect only when the application programs a non zero value to this register. The value programmed must conform to the guidelines described in 'FIFO RAM Allocation'. The core does not have any corrective logic if the FIFO sizes are programmed incorrectly. |
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| B |
RW |
EPINFOBASEADDR |
This field provides the start address of the EP info controller. The EP info controller manages the stored values in the last few locations of the SPRAM as listed below. - Host Buffer DMA mode: One location per channel is used in SPRAM to store the HCDMAn value. - Host Scatter/Gather DMA mode: Four locations per channel are used in SPRAM to store the Base Descriptor address, Current Descriptor address, Current Buffer Pointer, and the Status Quadlet. - Device Buffer DMA mode: One location per endpoint direction is used in SPRAM to store the DIEPDMA and DOEPDMA value. - Device Scatter/Gather DMA mode: Four locations per endpoint direction are used in SPRAM to store the Base Descriptor address, Current Descriptor address, Current Buffer Pointer and the Status Quadlet. |
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