Address offset: 0x7A1
Trigger Data 1
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | C | C | C | C | B | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A |
RW |
DATA |
Trigger Specific Data, refer to the RISC-V Debug Specification for more details. |
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| B |
RW |
DMODE |
Debug Mode This bit is only writable from Debug Mode |
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|
BOTH |
0 |
Both Debug and M-mode can write the tdata registers at the selected tselect. |
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|
ONLYDEBUG |
1 |
Only Debug Mode can write the tdata registers at the selected tselect. Writes from other modes are ignored. |
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| C |
RW |
TYPE |
Type |
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|
NOTRIGGER |
0x0 |
There is no trigger at this tselect |
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|
MATCH |
0x2 |
The trigger is an address match trigger. The remaining bits in this register act as described in mcontrol |
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