MCAUSE

Address offset: 0x342

Machine Cause

When a trap is taken into M-mode, mcause is written with a code indicating the event that caused the trap. Otherwise, mcause is never written by the implementation, though it may be explicitly written by software.

Note: Writing this register can have side effects, so care needs to be taken when initializing this for a new thread context. To be safe, initialize this to the reset value when creating a new thread.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				F	E	D	D	C				B	B	B	B	B	B	B	B					A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x30000000				0	0	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EXCEPTIONCODE										Exception code See RISC-V Instruction Set Manual Volume II: Privileged Architecture for details on the exception codes. Exception codes listed here only apply if the trap is not caused by an interrupt (Interrupt bitfield set to 0)
			INSTADDRMISALIGN	0x0								Instruction Address Misaligned
			INSTACCESSFAULT	0x1								Instruction Access Fault
			ILLEGALINST	0x2								Illegal Instruction
			BKPT	0x3								Breakpoint
			LOADADDRMISALIGN	0x4								Load Address Misaligned
			LOADACCESSFAULT	0x5								Load Access Fault
			STOREADDRMISALIGN	0x6								Store/AMO Address Misaligned
			STOREACCESSFAULT	0x7								Store/AMO Access Fault
			ECALLMMODE	0xB								Environment Call M-Mode
			MISALIGNSTACKING	0x18								Misaligned Stacking
			BUSFAULTSTACKING	0x19								Bus Fault on Stacking
			INTVECTORFAULT	0x1A								Interrupt Vector Fault
			MISALIGNUNSTACKING	0x1B								Misaligned Unstacking
			BUSFAULTUNSTACKING	0x1C								Bus Fault on Unstacking
			STORETIMEOUTFAULT	0x1D								Store Timeout Fault
			LOADTIMEOUTFAULT	0x1E								Load Timeout Fault
			STACKINGEXCFAULT	0x1F								Fault on Exception Stacking
B	RW	MPIL										Previous interrupt level
C	RW	MPIE										Previous interrupt enable, same as MSTATUS.MPIE
D	R	MPP										Previous privilege mode, same as MSTATUS.MPP
E	RW	MINHV										In hardware vectoring Set by hardware at start of hardware vectoring, cleared by hardware at end of successful hardware vectoring
F	RW	INTERRUPT										Interrupt bit Set if the trap was caused by an interrupt
			EXCEPTION	0
			INTERRUPT	1