FILTER.SAMPLEDELAY

Address offset: 0x538

Input Data Sampling with Number of ckFilterL (double frequency of PDM_CLK) Clock Cycle Delay. Optionally,input sample point can be delayed independently on left and right channels using FILTER:CTRL[20:19] bits


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	DELAY										Input Data Sampling with Number of ckFilterL (double frequency of PDM_CLK) Clock Cycle Delay
			NoDelay	0								No delay
			Delay1Ck	1								1 Cycle