Address offset: 0x080
Controls instruction trace filtering.
Might ignore writes when the trace unit is enabled or not idle.
Only returns stable data when TRCSTATR.PMSTABLE == 1.
Must be programmed, particularly to set the value of the SSSTATUS bit, which sets the state of the start/stop logic.
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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| ID | L | K | J | I | H | G | F | E | D | C | B | A | A | A | A | A | |||||||||||||||||||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A |
RW |
EVENT_SEL |
Select which resource number should be filtered. |
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Disabled |
0 |
This event is not filtered. |
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Enabled |
1 |
This event is filtered. |
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| B |
RW |
SSSTATUS |
When TRCIDR4.NUMACPAIRS > 0 or TRCIDR4.NUMPC > 0, this bit returns the status of the start/stop logic. |
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|
Stopped |
0 |
The start/stop logic is in the stopped state. |
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Started |
1 |
The start/stop logic is in the started state. |
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| C |
RW |
TRCRESET |
Controls whether a trace unit must trace a Reset exception. |
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Disabled |
0 |
The trace unit does not trace a Reset exception unless it traces the exception or instruction immediately prior to the Reset exception. |
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Enabled |
1 |
The trace unit always traces a Reset exception. |
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| D |
RW |
TRCERR |
When TRCIDR3.TRCERR==1, this bit controls whether a trace unit must trace a System error exception. |
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Disabled |
0 |
The trace unit does not trace a System error exception unless it traces the exception or instruction immediately prior to the System error exception. |
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Enabled |
1 |
The trace unit always traces a System error exception, regardless of the value of ViewInst. |
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| E-H |
RW |
EXLEVEL[i]_S (i=0..3) |
In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level i. |
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Disabled |
1 |
The trace unit does not generate instruction trace, in Secure state, for Exception level i. |
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Enabled |
0 |
The trace unit generates instruction trace, in Secure state, for Exception level i. |
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| I-L |
RW |
EXLEVEL[i]_NS (i=0..3) |
In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level i. |
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Disabled |
1 |
The trace unit does not generate instruction trace, in Non-secure state, for Exception level i. |
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Enabled |
0 |
The trace unit generates instruction trace, in Non-secure state, for Exception level i. |
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