Address offset: 0x514
Standby mode configuration
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ID | A | A | |||||||||||||||||||||||||||||||||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A |
RW |
MODE |
RRAM standby mode |
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|
Normal |
0 |
The RRAM automatically goes into idle mode while the RRAM is not being accessed The MCU power domain is turned off. |
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|
PowerDown |
2 |
The RRAM goes into power down mode when the access timeout counter is expired The penalty for RRAM access during wakeup from PowerDown mode is about 6us |
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|
Standby |
3 |
The RRAM remains active while the RRAM is not being accessed. Access to RRAM has the lowest latency when MCU PD is in RUN state, for example by using Constant Latency sub-power mode. ACCESSTIMEOUT has no effect in this mode. |
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