Address offset: 0x514 + (n × 0x18)
Host Channel DMA Address Register 0
This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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| ID | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
| Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A |
RW |
DMAADDR |
In Buffer DMA Mode: [31:0]: DMA Address (DMAAddr) This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. Reset: X if not programmed as the register is in SPRAM. In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous: [31:9]: DMA Address (DMAAddr) The start address must be 512-bytes aligned. This field holds the start address of the 512 bytes page. The first descriptor in the list must be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value. [8:3]: Current Transfer Desc(CTD) This value is in terms of number of descriptors. The values can be from 0 to 63. This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core starts processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr. [2:0]: Reserved In Scatter-Gather DMA (DescDMA) Mode for Isochronous: [31:N]: DMA Address (DMAAddr) The start address must be 512-bytes aligned. This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows: - [31:N]: Base Address - [N-1:3]: Offset - [2:0]: 000 For HS ISOC, if nTD is, - 7, N=6 - 15, N=7 - 31, N=8 - 63, N=9 - 127, N=10 - 255, N=11 For FS ISOC, if nTD is, - 1, N=4 - 3, N=5 - 7, N=6 - 15, N=7 - 31, N=8 - 63, N=9 [N-1:3]: Current Transfer Desc(CTD) CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application. Reset: (N+1:3)'h0 [2:0]: Reserved |
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