HPRT

R

PRTCONNSTS

Port Connect Status (PrtConnSts)

- 0: No device is attached to the port. - 1: A device is attached to the port.

RW

PRTCONNDET

Port Connect Detected (PrtConnDet)

The core sets this bit when a device connection is detected to trigger an interrupt to the application using the Host Port Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt).This bit can be set only by the core and the application must write 1 to clear it.The application must write a 1 to this bit to clear the interrupt.

RW

PRTENA

Port Enable (PrtEna)

A port is enabled only by the core after a reset sequence, and is disabled by an overcurrent condition, a disconnect condition, or by the application clearing this bit. The application cannot Set this bit by a register write. It can only clear it to disable the port by writing 1. This bit does not trigger any interrupt to the application.

RW

PRTENCHNG

Port Enable/Disable Change (PrtEnChng)

The core sets this bit when the status of the Port Enable bit [2] of this register changes.This bit can be set only by the core and the application must write 1 to clear it.

R

PRTOVRCURRACT

Port Overcurrent Active (PrtOvrCurrAct)

Indicates the overcurrent condition of the port.

RW

PRTOVRCURRCHNG

Port Overcurrent Change (PrtOvrCurrChng)

The core sets this bit when the status of the Port Overcurrent Active bit (bit 4) in this register changes.This bit can be set only by the core and the application must write 1 to clear it

RW

PRTRES

Port Resume (PrtRes)

The application sets this bit to drive resume signaling on the port. The core continues to drive the resume signal until the application clears this bit. If the core detects a USB remote wakeup sequence, as indicated by the Port Resume/Remote Wakeup Detected Interrupt bit of the Core Interrupt register (GINTSTS.WkUpInt), the core starts driving resume signaling without application intervention and clears this bit when it detects a disconnect condition. The read value of this bit indicates whether the core is currently driving resume signaling. When LPM is enabled, In L1 state the behavior of this bit is as follows: The application sets this bit to drive resume signaling on the port. The core continues to drive the resume signal until a pre-determined time specified in GLPMCFG.HIRD_Thres[3:0] field. If the core detects a USB remote wakeup sequence, as indicated by the Port L1Resume/Remote L1Wakeup Detected Interrupt bit of the Core Interrupt register (GINTSTS.L1WkUpInt), the core starts driving resume signaling without application intervention and clears this bit at the end of resume.This bit can be set by both core or application and also cleared by core or application. This bit is cleared by the core even if there is no device connected to the Host.

RW

PRTSUSP

Port Suspend (PrtSusp)

The application sets this bit to put this port in Suspend mode. The core only stops sending SOFs when this is Set. To stop the PHY clock, the application must Set the Port Clock Stop bit, which asserts the suspend input pin of the PHY. The read value of this bit reflects the current suspend status of the port. This bit is cleared by the core after a remote wakeup signal is detected or the application sets the Port Reset bit or Port Resume bit in this register or the Resume/Remote Wakeup Detected Interrupt bit or Disconnect Detected Interrupt bit in the Core Interrupt register (GINTSTS.WkUpInt or GINTSTS.DisconnInt, respectively).This bit is cleared by the core even if there is no device connected to the Host.

RW

PRTRST

Port Reset (PrtRst)

When the application sets this bit, a reset sequence is started on this port. The application must time the reset period and clear this bit after the reset sequence is complete. The application must leave this bit set for at least a minimum duration mentioned below to start a reset on the port. The application can leave it set for another 10 ms in addition to the required minimum duration, before clearing the bit, even though there is no maximum limit Set by the USB standard.This bit is cleared by the core even if there is no device connected to the Host. - High speed: 50 ms - Full speed/Low speed: 10 ms

R

PRTLNSTS

Port Line Status (PrtLnSts)

Indicates the current logic level USB data lines

RW

PRTPWR

Port Power (PrtPwr)

The application uses this field to control power to this port (write 1'b1 to set to 1'b1 and write 1'b0 to set to 1'b0), and the core can clear this bit on an over current condition. Note: This bit is interface independent. The application needs to program this bit for all interfaces as described in the host programming flow in the Programming Guide.

RW

PRTTSTCTL

Port Test Control (PrtTstCtl)

The application writes a nonzero value to this field to put the port into a Test mode, and the corresponding pattern is signaled on the port. To move the DWC_otg controller to test mode, you must set this field. Complete the following steps to move the DWC_otg core to test mode: - 1. Power on the core. - 2. Load the DWC_otg driver. - 3. Connect an HS device and enumerate to HS mode. - 4. Access the HPRT register to send test packets. - 5. Remove the device and connect to fixture (OPT) port. The DWC_otg host core continues sending out test packets. - 6. Test the eye diagram.

R

PRTSPD

Port Speed (PrtSpd)

Indicates the speed of the device attached to this port.