PCGCCTL

Address offset: 0xE00

Power and Clock Gating Control Register

This register is used to control the Power and Clock Gating characteristics of the controller.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				I	I	I	I	I	I	I	I	I	I	I	I	I	I	I	I	I	I	H				G		F	E	D		C		B	A
Reset 0x880A0000				1	0	0	0	1	0	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	STOPPCLK										Stop Pclk (StopPclk) - The application sets this bit to stop the PHY clock (phy_clk) when the USB is suspended, the session is not valid, or the device is disconnected. - The application clears this bit when the USB is resumed or a new session starts.
			DISABLED	0								Disable Stop Pclk
			ENABLED	1								Enable Stop Pclk
B	RW	GATEHCLK										Gate Hclk (GateHclk) - The application sets this bit to gate hclk to modules other than the AHB Completer and Requester and wakeup logic when the USB is suspended or the session is not valid. - The application clears this bit when the USB is resumed or a new session starts.
			DISABLED	0								Clears this bit when the USB is resumed or a new session starts
			ENABLED	1								Sets this bit to gate hclk to modules when the USB is suspended or the session is not valid
C	RW	RSTPDWNMODULE										Reset Power-Down Modules (RstPdwnModule) This bit is valid only in Partial Power-Down mode. - The application sets this bit when the power is turned off. - The application clears this bit after the power is turned on and the PHY clock is up. Note: The R/W of all core registers are possible only when this bit is set to 1b0.
			ON	0								Power is turned on
			OFF	1								Power is turned off
D	RW	ENBLL1GATING										Enable Sleep Clock Gating If this bit is set, core internal clock gating is enabled sleep state if utmi_l1_suspend_n cannot be asserted by the core. The PHY clock is not gated in sleep state if Enbl_L1Gating is not set.
			DISABLED	0								The PHY clock is not gated in Sleep state
			ENABLED	1								The Core internal clock gating is enabled in Sleep state
E	R	PHYSLEEP										PHY In Sleep Indicates that the PHY is in Sleep State.
			INACTIVE	0								Phy not in Sleep state
			ACTIVE	1								Phy in Sleep state
F	R	L1SUSPENDED										L1 Deep Sleep Indicates that the PHY is in deep sleep when in L1 state.
			INACTIVE	0								Non Deep Sleep
			ACTIVE	1								Deep Sleep
G	RW	RESTOREMODE										Restore Mode (RestoreMode) The application must program this bit to specify the restore mode during RESTORE POINT before programming PCGCCTL.EssRegRest bit is set. - Host Mode: - Device Mode:
			DISABLED	0								In Host mode,this bit indicates Host-initiated Resume and Reset. In Device mode, this bit indicates Device-initiated Remote Wakeup
			ENABLED	1								In Host mode,this bit indicates Device-initiated Remote Wakeup. In Device mode, this bit indicates Host-initiated Resume and Reset
H	W	ESSREGRESTORED										Essential Register Values Restored (EssRegRestored) A write of one into this field indicates that register values of essential registers have been restored. For definition of essential registers, refer programming flow section for Hibernation.
			NOTRESTORED	0								Register values of essential registers are not restored
			RESTORED	1								Register values of essential registers have been restored
I	RW	RESTOREVALUE										Restore Value (RestoreValue) When Hibernation mode is enabled, the RestoreValue needs to be read at SAVE_POINT to store in non-volatile memory and at RESTORE_POINT restored before PCGCCTL.EssRegRestored field is set. - [31] if_dev_mode -- 1: Device mode, core restored as device -- 0: Host mode, core restored as host - [30:29] p2hd_prt_spd (PRT speed) -- 00: HS -- 01: FS -- 10: LS -- 11: Reserved - [28:27] p2hd_dev_enum_spd (Device enumerated speed) -- 00: HS -- 01: FS (30/60 MHz clk) -- 10: LS -- 11: FS (48 MHz clk) - [26:20] mac_dev_addr (MAC device address) Device address - [19] mac_termselect (Termination selection) -- 0: HS_TERM (Program for High Speed) -- 1: FS_TERM (Program for Full Speed) - [18:17] mac_xcvrselect (Transceiver select) -- 00: HS_XCVR (High Speed) -- 01: FS_XCVR (Full Speed) -- 10: LS_XCVR (Low Speed) -- 11: LFS_XCVR (Reserved) - [16] sh2pl_prt_ctl[0] -- 1: prt_power enabled -- 0: prt_power disabled - [15:14] prt_clk_sel (Refer prt_clk_sel table) Defines port clock select for different speeds.