Address offset: 0x7B0
Debug Control and Status
This register is only accesible from debug mode
| Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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| ID | F | F | F | F | E | D | C | C | C | B | A | A | |||||||||||||||||||||||
| Reset 0x40000003 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | |||
| ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
| A |
R |
PRV |
Privilege level Contains the privilege level the hart was operating in when Debug Mode was entered. VPR only supports Machine Privilege Level. |
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MACHINE |
3 |
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| B |
RW |
STEP |
Step When set and not in Debug Mode, the hart will only execute a single instruction and then enter Debug Mode. If the instruction does not complete due to an exception, the hart will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set. The debugger must not change the value of this bit while the hart is running |
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| C |
R |
CAUSE |
Debug Mode enter cause When there are multiple reasons to enter Debug Mode in a single cycle, hardware should set cause to the cause with the highest priority. Values other than the following are reserved for future use |
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EBREAK |
1 |
An ebreak instruction was executed. (priority 3) |
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TRIGGER |
2 |
The Trigger Module caused a breakpoint exception. (priority 4, highest) |
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HALTREQ |
3 |
The debugger requested entry to Debug Mode using haltreq. (priority 1) |
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STEP |
4 |
The hart single stepped because step was set. (priority 0, lowest) |
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RESETHALTREQ |
5 |
The hart halted directly out of reset due to resethaltreq. It is also acceptable to report 3 when this happens. (priority 2) |
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| D |
RW |
STEPIE |
Step Interrupt Enable The debugger must not change the value of this bit while the hart is running |
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Disabled |
0 |
Interrupts are disabled during single stepping |
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Enabled |
1 |
Interrupts are enabled during single stepping. Implementations may hard wire this bit to 0. In that case interrupt behavior can be emulated by the debugger. |
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| E |
RW |
EBREAKM |
M-mode ebreak |
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SPEC |
0 |
ebreak instructions in M-mode behave as described in the Privileged Spe |
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ENTERDBG |
1 |
ebreak instructions in M-mode enter Debug Mode |
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| F |
R |
XDEBUGVER |
External Debug version |
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STDDBG |
4 |
External debug support exists as it is described in this document |
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