CONFIG.SCK.SRC

Address offset: 0x51C

SCK clock source selection


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																											B								A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CLKSRC										Clock source selection
			PCLK	0								Peripheral clock (instantiation table shows the TDM PCLK frequency)
			ACLK	1								Audio PLL clock
B	RW	BYPASS										Bypass clock generator. SCK will be equal to source input. If bypass is enabled the SCKFREQ setting has no effect.
			Disable	0								Disable bypass
			Enable	1								Enable bypass