NORDIC.CACHE.CTRL

Address offset: 0x7C8

Cache control


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																			B																A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ENABLE										Enable cache
			Disabled	0								Cache disabled
			Enabled	1								Cache enabled
B	RW W1S	CACHECLR										Cache clear Writing this bit writes the tag cache region to 0. This should be done before enabling the cache. The CPU stalls until the operation is complete. Interrupts must be disabled when performing the cache clear operation.
			NoOperation	0								No Operation
			Clear	1								Cache clear