DSTS

Address offset: 0x808

Device Status Register

This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from Device All Interrupts (DAINT) register.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID												E	E	D	D	D	D	D	D	D	D	D	D	D	D	D	D					C	B	B	A
Reset 0x00000002				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0
ID	R/W	Field	Value ID	Value								Description
A	R	SUSPSTS										Suspend Status (SuspSts) In Device mode, this bit is set as long as a Suspend condition is detected on the USB. The core enters the Suspend state when there is no activity on the phy_line_state_i signal for an extended period of time. The core comes out of the suspend under the following conditions : - If there is any activity on the phy_line_state_i signal, or - If the application writes to the Remote Wakeup Signaling bit in the Device Control register (DCTL.RmtWkUpSig). When the core comes out of the suspend, this bit is set to 1'b0.
			INACTIVE	0								No suspend state
			ACTIVE	1								Suspend state
B	R	ENUMSPD										Enumerated Speed (EnumSpd) Indicates the speed at which the controller has come up after speed detection through a connect or reset sequence. Low speed is not supported for devices using a UTMI+ PHY.
			HS3060	0								High speed (PHY clock is running at 30 or 60 MHz)
			FS3060	1								Full speed (PHY clock is running at 30 or 60 MHz)
			LS6	2								Low speed (PHY clock is running at 6 MHz)
			FS48	3								Full speed (PHY clock is running at 48 MHz)
C	R	ERRTICERR										Erratic Error (ErrticErr) The core sets this bit to report any erratic errors (phy_rxvalid_i/phy_rxvldh_i or phy_rxactive_i is asserted for at least 2 ms, due to PHY error) seen on the UTMI+. Due to erratic errors, the core goes into Suspended state and an interrupt is generated to the application with Early Suspend bit of the Core Interrupt register (GINTSTS.ErlySusp). If the early suspend is asserted due to an erratic error, the application must perform a PHY reset followed by a soft reset to controller.
			INACTIVE	0								No Erratic Error
			ACTIVE	1								Erratic Error
D	R	SOFFN										Frame or Microframe Number of the Received SOF (SOFFN) When the core is operating at high speed, this field contains a microframe number. When the core is operating at full or low speed, this field contains a Frame number. Note: This register may return a non-zero value if read immediately after power-on reset. In case the register bit reads non-zero immediately after power-on reset, it does not indicate that SOF has been received from the host. The read value of this interrupt is valid only after a valid connection between host and device is established.
E	R	DEVLNSTS										Device Line Status (DevLnSts) Indicates the current logic level USB data lines - DevLnSts[1]: Logic level of D- - DevLnSts[0]: Logic level of D+