The domain configuration (DCNF) peripheral enables identification of the CPU by its CPU ID in the device (CPUID). It also provides protection of the AHB multilayer interconnect (AMLI).

AMLI protection is enabled through the DCNF configuration registers that can block some paths from the AHB masters to their respective AHB slaves in the AMLI.

For an illustration of how the AHB masters and slaves are connected through the AMLI, see Memory.

Protection

DCNF protection blocks the path of AHB masters in an external core from accessing AHB slaves in the AMLI of the local core. Essentially, blocking external core access to internal resources of the local core.

The following figure is a simplified version of the AMLI that shows the set of configuration registers used to control this behavior. A more detailed AMLI figure can be found in Memory.
Figure 1. Domain configuration
Page-1 Sheet.1 AHB Multilayer Interconnect External side AHB Multilayer InterconnectExternal side Sheet.3 DCNF EXTPERI[0] DCNFEXTPERI[0] Sheet.4 DCNF EXTCODE[0] DCNFEXTCODE[0] Sheet.5 DCNF EXTRAM[0] DCNFEXTRAM[0] Sheet.13 Sheet.21 Sheet.24 Page 1 Page 1 Sheet.25 Page 2 Page 2 Sheet.26 ... ... Sheet.27 Page N Page N Sheet.28 0x0000 0000 0x0000 0000 Sheet.64 RAM0 AHB slave RAM0AHB slave Sheet.65 Section 0 Section 0 Sheet.67 0x2000 0000 0x2000 0000 Sheet.69 Sheet.70 Dynamic connector.226 Dynamic connector.231 Dynamic connector.83 Dynamic connector.235 Dynamic connector.89 Sheet.112 External core Externalcore Sheet.113 AHB Master AHB Master Dynamic connector.281 Sheet.115 Sheet.116 Sheet.140 Sheet.141 Sheet.142 Sheet.143 Sheet.144 Sheet.145 Sheet.146 Sheet.147 Sheet.148 Sheet.149 Sheet.150 Sheet.151 Sheet.152 Sheet.162 Dynamic connector.298 Sheet.169 CODE0 AHB slave CODE0AHB slave Dynamic connector.319 Sheet.193 Sheet.194 Sheet.195 Sheet.202 Sheet.203 Sheet.204 Sheet.215 SLAVEn SLAVEn Sheet.216 SLAVE1 SLAVE1 Sheet.217 SLAVE0 SLAVE0 Sheet.218 SLAVE0 SLAVE0 Sheet.249 Page 0 Page 0 Sheet.278 SLAVE0 SLAVE0 Sheet.333 Section 1 Section 1 Sheet.334 ... ... Sheet.335 Section N Section N Sheet.336 RAM1 AHB slave RAM1AHB slave Sheet.337 Section 0 Section 0 Sheet.339 Section 1 Section 1 Sheet.341 Section N Section N Sheet.342 RAMn AHB slave RAMnAHB slave Sheet.343 Section 0 Section 0 Sheet.344 < 0.5 GB RAM < 0.5 GB RAM Sheet.345 Section 1 Section 1 Sheet.347 Section N Section N Dynamic connector.378 Dynamic connector.379 Sheet.391 ... ... Sheet.392 ... ... Sheet.393 < 0.5 GB CODE < 0.5 GB CODE Sheet.394 PERI APB slave PERIAPB slave Sheet.395 APB Peripherals APB Peripherals Sheet.397 Dynamic connector.398

The DCNF configuration registers that enable the DCNF protection are the following:

An attempt to access the blocked resources will trigger a BusFault or a HardFault exception, depending on the value of the BUSFAULTENA bit in the Arm® Cortex®-M33 SHCSR (system handler control and state register). This is described in the Arm Cortex-M33 Devices Generic User Guide.

RAM protection

RAM regions are protected by configuring the SLAVE bits in the register EXTRAM[n].PROTECT of the equivalent master port.

Peripheral protection

Peripheral memory regions are protected by configuring the SLAVE bits in the register EXTPERI[n].PROTECT of the equivalent master port.

Code protection

Code memory regions are protected by configuring the SLAVE bits in the register EXTCODE[0].PROTECT of the equivalent master port.

Registers

Instances

Instance Domain Base address TrustZone Split access Description
Map Att DMA

DCNF : S
DCNF : NS

 APPLICATION

0x50000000
0x40000000

 US S NA No

Domain configuration
DCNF NETWORK 0x41000000 HF NS NA No

Domain configuration

Configuration

Instance Domain Configuration

DCNF : S
DCNF : NS

 APPLICATION

CPUID value is 0x00000000
DCNF NETWORK

Registers EXTPERI[n].PROTECT, EXTRAM[n].PROTECT, and EXTCODE[n].PROTECT not available for the network core.

CPUID value is 0x00000001

Register overview

Register Offset TZ Description
CPUID 0x420

CPU ID of this subsystem
EXTPERI[n].PROTECT 0x440

Control access for master connected to AMLI master port EXTPERI[n]
EXTRAM[n].PROTECT 0x460

Control access from master connected to AMLI master port EXTRAM[n]
EXTCODE[n].PROTECT 0x480

Control access from master connected to AMLI master port EXTCODE[n]

CPUID

Address offset: 0x420

CPU ID of this subsystem

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

R

CPUID

CPU ID

EXTPERI[n].PROTECT (n=0..0)

Address offset: 0x440 + (n × 0x4)

Control access for master connected to AMLI master port EXTPERI[n]

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

SLAVE[i] (i=0..0)

Control access to slave i of master EXTPERI[n]

Allowed

0

Access to slave is allowed

Blocked

1

Access to slave is blocked

EXTRAM[n].PROTECT (n=0..0)

Address offset: 0x460 + (n × 0x4)

Control access from master connected to AMLI master port EXTRAM[n]

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A-H

RW

SLAVE[i] (i=0..7)

Control access to slave i of master EXTRAM[n]

Allowed

0

Access to slave is allowed

Blocked

1

Access to slave is blocked

EXTCODE[n].PROTECT (n=0..0)

Address offset: 0x480 + (n × 0x4)

Control access from master connected to AMLI master port EXTCODE[n]

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

SLAVE[i] (i=0..0)

Control access to slave i of master EXTCODE[n]

Allowed

0

Access to slave is allowed

Blocked

1

Access to slave is blocked