FPU — Floating point unit (FPU) exceptions

The Arm® Cortex®-M33 has FPU signals that indicate mathematical errors that cause floating-point exceptions.

The FPU signals are routed to the following event registers:

FPUIOC: INVALIDOPERATION
FPUIDC: DENORMALINPUT
FPUOFC: OVERFLOW
FPUUFC: UNDERFLOW
FPUDZC: DIVIDEBYZERO
FPUIXC: INEXACT

To clear the FPU exception source, write a 0 to the Arm Cortex-M33 FPSCR (floating-point status control register), as described in the Arm Cortex-M33 Devices Generic User Guide.

Registers

Instances


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
FPU : S FPU : NS	APPLICATION	0x50000000 0x40000000	US	S	NA	No	Floating Point unit interrupt control

Register overview


Register	Offset	Description
EVENTS_INVALIDOPERATION	0x100	An FPUIOC exception triggered by an invalid operation has occurred in the FPU
EVENTS_DIVIDEBYZERO	0x104	An FPUDZC exception triggered by a floating-point divide-by-zero operation has occurred in the FPU
EVENTS_OVERFLOW	0x108	An FPUOFC exception triggered by a floating-point overflow has occurred in the FPU
EVENTS_UNDERFLOW	0x10C	An FPUUFC exception triggered by a floating-point underflow has occurred in the FPU
EVENTS_INEXACT	0x110	An FPUIXC exception triggered by an inexact floating-point operation has occurred in the FPU
EVENTS_DENORMALINPUT	0x114	An FPUIDC exception triggered by a denormal floating-point input has occurred in the FPU
INTEN	0x300	Enable or disable interrupt
INTENSET	0x304	Enable interrupt
INTENCLR	0x308	Disable interrupt

EVENTS_INVALIDOPERATION

Address offset: 0x100

An FPUIOC exception triggered by an invalid operation has occurred in the FPU


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_INVALIDOPERATION										An FPUIOC exception triggered by an invalid operation has occurred in the FPU
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_DIVIDEBYZERO

Address offset: 0x104

An FPUDZC exception triggered by a floating-point divide-by-zero operation has occurred in the FPU


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_DIVIDEBYZERO										An FPUDZC exception triggered by a floating-point divide-by-zero operation has occurred in the FPU
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_OVERFLOW

Address offset: 0x108

An FPUOFC exception triggered by a floating-point overflow has occurred in the FPU


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_OVERFLOW										An FPUOFC exception triggered by a floating-point overflow has occurred in the FPU
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_UNDERFLOW

Address offset: 0x10C

An FPUUFC exception triggered by a floating-point underflow has occurred in the FPU


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_UNDERFLOW										An FPUUFC exception triggered by a floating-point underflow has occurred in the FPU
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_INEXACT

Address offset: 0x110

An FPUIXC exception triggered by an inexact floating-point operation has occurred in the FPU


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_INEXACT										An FPUIXC exception triggered by an inexact floating-point operation has occurred in the FPU
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_DENORMALINPUT

Address offset: 0x114

An FPUIDC exception triggered by a denormal floating-point input has occurred in the FPU


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_DENORMALINPUT										An FPUIDC exception triggered by a denormal floating-point input has occurred in the FPU
			NotGenerated	0								Event not generated
			Generated	1								Event generated

INTEN

Address offset: 0x300

Enable or disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																														F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	INVALIDOPERATION										Enable or disable interrupt for event INVALIDOPERATION
			Disabled	0								Disable
			Enabled	1								Enable
B	RW	DIVIDEBYZERO										Enable or disable interrupt for event DIVIDEBYZERO
			Disabled	0								Disable
			Enabled	1								Enable
C	RW	OVERFLOW										Enable or disable interrupt for event OVERFLOW
			Disabled	0								Disable
			Enabled	1								Enable
D	RW	UNDERFLOW										Enable or disable interrupt for event UNDERFLOW
			Disabled	0								Disable
			Enabled	1								Enable
E	RW	INEXACT										Enable or disable interrupt for event INEXACT
			Disabled	0								Disable
			Enabled	1								Enable
F	RW	DENORMALINPUT										Enable or disable interrupt for event DENORMALINPUT
			Disabled	0								Disable
			Enabled	1								Enable

INTENSET

Address offset: 0x304

Enable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																														F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	INVALIDOPERATION										Write '1' to enable interrupt for event INVALIDOPERATION
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW	DIVIDEBYZERO										Write '1' to enable interrupt for event DIVIDEBYZERO
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
C	RW	OVERFLOW										Write '1' to enable interrupt for event OVERFLOW
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
D	RW	UNDERFLOW										Write '1' to enable interrupt for event UNDERFLOW
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
E	RW	INEXACT										Write '1' to enable interrupt for event INEXACT
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
F	RW	DENORMALINPUT										Write '1' to enable interrupt for event DENORMALINPUT
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																														F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	INVALIDOPERATION										Write '1' to disable interrupt for event INVALIDOPERATION
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW	DIVIDEBYZERO										Write '1' to disable interrupt for event DIVIDEBYZERO
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
C	RW	OVERFLOW										Write '1' to disable interrupt for event OVERFLOW
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
D	RW	UNDERFLOW										Write '1' to disable interrupt for event UNDERFLOW
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
E	RW	INEXACT										Write '1' to disable interrupt for event INEXACT
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
F	RW	DENORMALINPUT										Write '1' to disable interrupt for event DENORMALINPUT
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled