To ensure good RF performance when designing PCBs, it is highly recommended to use the PCB layouts and component values provided by Nordic Semiconductor.

Documentation for the different package reference circuits, including Altium Designer files, PCB layout files, and PCB production files can be downloaded from www.nordicsemi.com.

In this section, there are reference circuits for QKAA aQFN™94, CLAA WLCSP, and CMAA WLCSP, showing the components and component values to support on-chip features in a design.

Some general guidance is summarized here:
  • External supply from VDD is only available when power is supplied to VDDH.
  • When supplying power from a USB source only, VBUS pin must be connected to VDDH pin if USB is to be used.
  • Components required for DC/DC function are only needed if DC/DC mode is enabled for that regulator.
  • NFC can be used in any configuration.
  • USB can be used in any configuration as long as VBUS is supplied by the USB host.
  • The schematics include an optional, but recommended, series resistor on the USB supply for improved immunity to transient over-voltage during VBUS connection.
Table 1. Circuit configurations for QKAA aQFN™94
Config no. Supply configuration Enabled features
VDDH VDD EXTSUPPLY DCDC on VREGH DCDC on VREGMAIN and VREGRADIO USB NFC
Config. 1 Battery/Ext. regulator N/A Yes Yes Yes Yes No
Config. 2 N/A Battery/Ext. regulator No No Yes Yes Yes
Config. 3 N/A Battery/Ext. regulator No No Yes No No
Config. 4 USB (VDDH = VBUS) N/A No No No Yes No
Table 2. Circuit configurations for CLAA WLCSP
Config no. Supply configuration Enabled features
VDDH VDD EXTSUPPLY DCDC on VREGH DCDC on VREGMAIN and VREGRADIO USB NFC
Config. 1 Battery/Ext. regulator N/A Yes Yes Yes Yes No
Config. 2 N/A Battery/Ext. regulator No No Yes Yes Yes
Config. 3 N/A Battery/Ext. regulator No No Yes No No
Config. 4 USB (VDDH = VBUS) N/A No No No Yes No
Table 3. Circuit configurations for CMAA WLCSP
Config no. Supply configuration Enabled features
VDDH VDD EXTSUPPLY DCDC on VREGH DCDC on VREGMAIN and VREGRADIO USB NFC
Config. 1 Battery/Ext. regulator N/A Yes Yes Yes Yes No
Config. 2 N/A Battery/Ext. regulator No No Yes Yes Yes
Config. 3 N/A Battery/Ext. regulator No No Yes No No
Config. 4 USB (VDDH = VBUS) N/A No No No Yes No

Circuit configuration no. 1 for QKAA aQFN94

Circuit configuration number 1 for QKAA aQFN™94 is showing the schematic and the bill of materials table.

Table 4. Configuration summary for circuit configuration no. 1
Config no. Supply configuration Enabled features
VDDH VDD EXTSUPPLY DCDC on VREGH DCDC on VREGMAIN and VREGRADIO USB NFC
Config. 1 Battery/Ext. regulator N/A Yes Yes Yes Yes No
Figure 1. Circuit configuration no. 1 schematic

image/svg+xmlXC1 XC2 VDD_nRF SWDCLK SWDIO RF P0.00/XL1 P0.01/XL2 X1 32MHz C4 2.2nF C2 1.0 µ F C6 100nF P0.19 P0.16/QSPI3 P0.17/QSPI_CLK L2 10 µ H C3 1.0 µ F C1 0.7pF P0.03/NFC2 P0.04/AIN0 VDD_nRF P0.18/QSPI_CS X2 32.768kHz Optional L4 10 µ H VDD_HV C8 100nF C19 2.2 µ F P0.08/TRACEDATA3 C9 100nF P0.22 C20 4.7 µ F P0.09/TRACEDATA2 P0.11/TRACEDATA0 P0.12/TRACECLK P0.13/QSPI0 P0.14/QSPI1 P0.20 P0.21 P0.23 P0.24 P0.25/AIN4 P0.05/AIN1 P0.06/AIN2 P0.07/AIN3 L3 10 µ H C7 1.0 µ F C16 1.0 µ F VDD_nRF C5 1.0 µ F P0.15/QSPI2 P0.02/NFC1 P0.26/AIN5 P0.27/AIN6 C17 4.7 µ F VBUS C18 4.7 µ F P1.00 P1.01 P1.02/I2C P1.03/I2C P1.04 P1.05 P1.06 P1.07 P1.08 P1.09 D_N D_P P0.28/AIN7 P0.30 P0.31 P0.29 RESET P0.10/TRACEDATA1 C10 100nF C11 100nF C12 100nF VDD_nRF VDD AJ31 DECRF G31 VDD N31 VDD AL11 DCC A21 DCCH J1 VBUS A5 DECUSB B6 VDD AL25 DECR A27 DCCD B10 DECD A15 VDD AL17 DECA A13 DECN A23 nRF5340 VDD L1 VDDH E1 VDD U1 VDD C1 VDD E31 VDD AL7 VDD AL3 VDD AC1 VDD A19 VDD B8 VDD AG1 VDD B28 ANT L31 XC1 C31 XC2 B30 SWDCLK W31 SWDIO AA31 D- B4 D+ B2 RESET AC31 U1A nRF5340-QKAA P0.00/XL1 N1 P0.01/XL2 R1 P0.26/AIN5 AL29 P0.27/AIN6 AK30 P0.06/AIN2 AB2 P0.08/TRACEDATA[3] AH2 P0.16/QSPI[3] AL9 P0.02/NFC1 W1 P0.20 AK16 P0.04/AIN0 V2 P0.05/AIN1 Y2 P0.22 AK18 P0.23 AK20 P0.24 AL27 P0.25/AIN4 AK28 P0.19 AL13 P0.17/QSPI_CLK AK12 P0.03/NFC2 AA1 P0.18/QSPI_CS AK14 P0.07/AIN3 AD2 P0.09/TRACEDATA[2] AJ1 P0.11/TRACEDATA[0] AK4 P0.12/TRACECLK AK6 P0.13/QSPI[0] AL5 P0.14/QSPI[1] AK8 P0.15/QSPI[2] AK10 P0.21 AL15 P0.28/AIN7 AE31 P0.30 B24 P0.31 B22 P0.29 U31 P0.10/TRACEDATA[1] AK2 U1B nRF5340-QKAA P1.11 B20 P1.10 R31 P1.09 AK26 P1.01 P2 P1.02/I2C AE1 P1.03/I2C AF2 P1.06 AL21 P1.07 AK24 P1.08 AL23 P1.12 B18 P1.13 A17 P1.14 B16 P1.15 B14 P1.00 M2 P1.05 AK22 P1.04 AL19 U1C nRF5340-QKAA P1.10 P1.11 P1.12 P1.13 P1.14 P1.15 C13 100nF C14 100nF C15 100nF R1 2R2 C21 N.C. L1 2.2nH ANT N.C. G1 N.C. B26 VSS_PAD 104 N.C. H2 N.C. B12 N.C. A25 N.C. J31 N.C. D2 N.C. F2 N.C. T2 N.C. AG31 N.C. A1 N.C. A31 N.C. AL1 N.C. AL31 U1D nRF5340-QKAA
Note: For PCB reference layouts, see the product page for the nRF5340 on www.nordicsemi.com.
Table 5. Bill of material for circuit configuration no. 1
Designator Value Description Footprint
C1 0.7 pF Capacitor, NP0, ±0.05 pF 0201
C2, C3, C5, C7, C16 1.0 µF Capacitor, X7S, ±10% 0402
C4 2.2 nF Capacitor, X7R, ±10% 0201
C6, C8, C9, C10, C11, C12, C13, C14, C15 100 nF Capacitor, X7S, ±10% 0201
C17, C20 4.7 µF Capacitor, X7S, ±10% 0603
C18 4.7 µF Capacitor, X7R, ±10% 0603
C19 2.2 µF Capacitor, X7R, ±10% 0603
C21 N.C. Not mounted 0201
L1 2.2 nH High frequency chip inductor, ±5% 0201
L2, L3 10 µH Inductor, 50 mA, ±20% 0603
L4 10 µH Inductor, 80 mA, ±20% 0603
R1 2.2 Ω Resistor, ±1%, 0.05 W 0201
U1 nRF5340-QKAA Multiprotocol Bluetooth® Low Energy, IEEE 802.15.4, ANT, and 2.4GHz proprietary System on Chip AQFN-94
X1 32 MHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: ±30 ppm. For frequency tolerance requirements, see 32 MHz crystal oscillator (HFXO). XTAL_2016
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

Circuit configuration no. 2 for QKAA aQFN94

Circuit configuration number 2 for QKAA aQFN™94 is showing the schematic and the bill of materials table.

Table 6. Configuration summary for circuit configuration no. 2
Config no. Supply configuration Enabled features
VDDH VDD EXTSUPPLY DCDC on VREGH DCDC on VREGMAIN and VREGRADIO USB NFC
Config. 2 N/A Battery/Ext. regulator No No Yes Yes Yes
Figure 2. Circuit configuration no. 2 schematic

image/svg+xmlXC1 XC2 VDD_nRF SWDCLK SWDIO RF P0.00/XL1 P0.01/XL2 X1 32MHz C4 2.2nF C2 1.0 µ F C6 100nF P0.19 P0.16/QSPI3 P0.17/QSPI_CLK L2 10 µ H C3 1.0 µ F C1 0.7pF P0.03/NFC2 P0.04/AIN0 VDD_nRF P0.18/QSPI_CS X2 32.768kHz Optional C8 100nF P0.08/TRACEDATA3 C9 100nF P0.22 P0.09/TRACEDATA2 P0.11/TRACEDATA0 P0.12/TRACECLK P0.13/QSPI0 P0.14/QSPI1 P0.20 P0.21 P0.23 P0.24 P0.25/AIN4 P0.05/AIN1 P0.06/AIN2 P0.07/AIN3 L3 10 µ H C7 1.0 µ F C16 1.0 µ F VDD_nRF C5 1.0 µ F P0.15/QSPI2 P0.02/NFC1 P0.26/AIN5 P0.27/AIN6 C17 4.7 µ F VBUS C18 4.7 µ F P1.00 P1.01 P1.02/I2C P1.03/I2C P1.04 P1.05 P1.06 P1.07 P1.08 P1.09 D_N D_P P0.28/AIN7 P0.30 P0.31 P0.29 RESET P0.10/TRACEDATA1 C10 100nF C11 100nF C12 100nF VDD_nRF VDD AJ31 DECRF G31 VDD N31 VDD AL11 DCC A21 DCCH J1 VBUS A5 DECUSB B6 VDD AL25 DECR A27 DCCD B10 DECD A15 VDD AL17 DECA A13 DECN A23 nRF5340 VDD L1 VDDH E1 VDD U1 VDD C1 VDD E31 VDD AL7 VDD AL3 VDD AC1 VDD A19 VDD B8 VDD AG1 VDD B28 ANT L31 XC1 C31 XC2 B30 SWDCLK W31 SWDIO AA31 D- B4 D+ B2 RESET AC31 U1A nRF5340-QKAA P0.00/XL1 N1 P0.01/XL2 R1 P0.26/AIN5 AL29 P0.27/AIN6 AK30 P0.06/AIN2 AB2 P0.08/TRACEDATA[3] AH2 P0.16/QSPI[3] AL9 P0.02/NFC1 W1 P0.20 AK16 P0.04/AIN0 V2 P0.05/AIN1 Y2 P0.22 AK18 P0.23 AK20 P0.24 AL27 P0.25/AIN4 AK28 P0.19 AL13 P0.17/QSPI_CLK AK12 P0.03/NFC2 AA1 P0.18/QSPI_CS AK14 P0.07/AIN3 AD2 P0.09/TRACEDATA[2] AJ1 P0.11/TRACEDATA[0] AK4 P0.12/TRACECLK AK6 P0.13/QSPI[0] AL5 P0.14/QSPI[1] AK8 P0.15/QSPI[2] AK10 P0.21 AL15 P0.28/AIN7 AE31 P0.30 B24 P0.31 B22 P0.29 U31 P0.10/TRACEDATA[1] AK2 U1B nRF5340-QKAA P1.11 B20 P1.10 R31 P1.09 AK26 P1.01 P2 P1.02/I2C AE1 P1.03/I2C AF2 P1.06 AL21 P1.07 AK24 P1.08 AL23 P1.12 B18 P1.13 A17 P1.14 B16 P1.15 B14 P1.00 M2 P1.05 AK22 P1.04 AL19 U1C nRF5340-QKAA P1.10 P1.11 P1.12 P1.13 P1.14 P1.15 C13 100nF C14 100nF C15 100nF C21 N.C. L1 2.2nH ANT CT1 CT3 Note: The value of CT1, CT2, CT3 and CT4 must be tuned to match the selected NFC antenna. CT2 CT4 R1 2R2 N.C. G1 N.C. B26 VSS_PAD 104 N.C. H2 N.C. B12 N.C. A25 N.C. J31 N.C. D2 N.C. F2 N.C. T2 N.C. AG31 N.C. A1 N.C. A31 N.C. AL1 N.C. AL31 U1D nRF5340-QKAA
Note: For PCB reference layouts, see the product page for the nRF5340 on www.nordicsemi.com.
Table 7. Bill of material for circuit configuration no. 2
Designator Value Description Footprint
C1 0.7 pF Capacitor, NP0, ±0.05 pF 0201
C2, C3, C5, C7, C16 1.0 µF Capacitor, X7S, ±10% 0402
C4 2.2 nF Capacitor, X7R, ±10% 0201
C6, C8, C9, C10, C11, C12, C13, C14, C15 100 nF Capacitor, X7S, ±10% 0201
C17 4.7 µF Capacitor, X7S, ±10% 0603
C18 4.7 µF Capacitor, X7R, ±10% 0603
C21 N.C. Not mounted 0201
CT1, CT2, CT3, CT4 Antenna dependent Capacitor, NP0, ±5% 0201
L1 2.2 nH High frequency chip inductor, ±5% 0201
L2, L3 10 µH Inductor, 50 mA, ±20% 0603
R1 2.2 Ω Resistor, ±1%, 0.05 W 0201
U1 nRF5340-QKAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4GHz proprietary System on Chip AQFN-94
X1 32 MHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: ±30 ppm. For frequency tolerance requirements, see 32 MHz crystal oscillator (HFXO). XTAL_2016
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

Circuit configuration no. 3 for QKAA aQFN94

Circuit configuration number 3 for QKAA aQFN™94 is showing the schematic and the bill of materials table.

Table 8. Configuration summary for circuit configuration no. 3
Config no. Supply configuration Enabled features
VDDH VDD EXTSUPPLY DCDC on VREGH DCDC on VREGMAIN and VREGRADIO USB NFC
Config. 3 N/A Battery/Ext. regulator No No Yes No No
Figure 3. Circuit configuration no. 3 schematic

image/svg+xmlXC1 XC2 VDD_nRF SWDCLK SWDIO RF P0.00/XL1 P0.01/XL2 X1 32MHz C4 2.2nF C2 1.0 µ F C6 100nF P0.19 P0.16/QSPI3 P0.17/QSPI_CLK L2 10 µ H C3 1.0 µ F C1 0.7pF P0.03/NFC2 P0.04/AIN0 VDD_nRF P0.18/QSPI_CS X2 32.768kHz Optional C8 100nF P0.08/TRACEDATA3 C9 100nF P0.22 P0.09/TRACEDATA2 P0.11/TRACEDATA0 P0.12/TRACECLK P0.13/QSPI0 P0.14/QSPI1 P0.20 P0.21 P0.23 P0.24 P0.25/AIN4 P0.05/AIN1 P0.06/AIN2 P0.07/AIN3 L3 10 µ H C7 1.0 µ F C16 1.0 µ F VDD_nRF C5 1.0 µ F P0.15/QSPI2 P0.02/NFC1 P0.26/AIN5 P0.27/AIN6 P1.00 P1.01 P1.02/I2C P1.03/I2C P1.04 P1.05 P1.06 P1.07 P1.08 P1.09 P0.28/AIN7 P0.30 P0.31 P0.29 RESET P0.10/TRACEDATA1 C10 100nF C11 100nF C12 100nF VDD_nRF VDD AJ31 DECRF G31 VDD N31 VDD AL11 DCC A21 DCCH J1 VBUS A5 DECUSB B6 VDD AL25 DECR A27 DCCD B10 DECD A15 VDD AL17 DECA A13 DECN A23 nRF5340 VDD L1 VDDH E1 VDD U1 VDD C1 VDD E31 VDD AL7 VDD AL3 VDD AC1 VDD A19 VDD B8 VDD AG1 VDD B28 ANT L31 XC1 C31 XC2 B30 SWDCLK W31 SWDIO AA31 D- B4 D+ B2 RESET AC31 U1A nRF5340-QKAA P0.00/XL1 N1 P0.01/XL2 R1 P0.26/AIN5 AL29 P0.27/AIN6 AK30 P0.06/AIN2 AB2 P0.08/TRACEDATA[3] AH2 P0.16/QSPI[3] AL9 P0.02/NFC1 W1 P0.20 AK16 P0.04/AIN0 V2 P0.05/AIN1 Y2 P0.22 AK18 P0.23 AK20 P0.24 AL27 P0.25/AIN4 AK28 P0.19 AL13 P0.17/QSPI_CLK AK12 P0.03/NFC2 AA1 P0.18/QSPI_CS AK14 P0.07/AIN3 AD2 P0.09/TRACEDATA[2] AJ1 P0.11/TRACEDATA[0] AK4 P0.12/TRACECLK AK6 P0.13/QSPI[0] AL5 P0.14/QSPI[1] AK8 P0.15/QSPI[2] AK10 P0.21 AL15 P0.28/AIN7 AE31 P0.30 B24 P0.31 B22 P0.29 U31 P0.10/TRACEDATA[1] AK2 U1B nRF5340-QKAA P1.11 B20 P1.10 R31 P1.09 AK26 P1.01 P2 P1.02/I2C AE1 P1.03/I2C AF2 P1.06 AL21 P1.07 AK24 P1.08 AL23 P1.12 B18 P1.13 A17 P1.14 B16 P1.15 B14 P1.00 M2 P1.05 AK22 P1.04 AL19 U1C nRF5340-QKAA P1.10 P1.11 P1.12 P1.13 P1.14 P1.15 C13 100nF C14 100nF C15 100nF C21 N.C. L1 2.2nH ANT N.C. G1 N.C. B26 VSS_PAD 104 N.C. H2 N.C. B12 N.C. A25 N.C. J31 N.C. D2 N.C. F2 N.C. T2 N.C. AG31 N.C. A1 N.C. A31 N.C. AL1 N.C. AL31 U1D nRF5340-QKAA
Note: For PCB reference layouts, see the product page for the nRF5340 on www.nordicsemi.com.
Table 9. Bill of material for circuit configuration no. 3
Designator Value Description Footprint
C1 0.7 pF Capacitor, NP0, ±0.05 pF 0201
C2, C3, C5, C7, C16 1.0 µF Capacitor, X7S, ±10% 0402
C4 2.2 nF Capacitor, X7R, ±10% 0201
C6, C8, C9, C10, C11, C12, C13, C14, C15 100 nF Capacitor, X7S, ±10% 0201
C21 N.C. Not mounted 0201
L1 2.2 nH High frequency chip inductor, ±5% 0201
L2, L3 10 µH Inductor, 50 mA, ±20% 0603
U1 nRF5340-QKAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4GHz proprietary System on Chip AQFN-94
X1 32 MHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: ±30 ppm. For frequency tolerance requirements, see 32 MHz crystal oscillator (HFXO). XTAL_2016
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

Circuit configuration no. 4 for QKAA aQFN94

Circuit configuration number 4 for QKAA aQFN™94 is showing the schematic and the bill of materials table.

Table 10. Configuration summary for circuit configuration no. 4
Config no. Supply configuration Enabled features
VDDH VDD EXTSUPPLY DCDC on VREGH DCDC on VREGMAIN and VREGRADIO USB NFC
Config. 4 USB (VDDH = VBUS) N/A No No No Yes No
Figure 4. Circuit configuration no. 4 schematic

image/svg+xmlXC1 XC2 VDD_nRF SWDCLK SWDIO RF P0.00/XL1 P0.01/XL2 X1 32MHz C4 2.2nF C2 1.0 µ F C6 100nF P0.19 P0.16/QSPI3 P0.17/QSPI_CLK C3 1.0 µ F C1 0.7pF P0.03/NFC2 P0.04/AIN0 VDD_nRF P0.18/QSPI_CS X2 32.768kHz Optional C8 100nF C19 2.2 µ F P0.08/TRACEDATA3 C9 100nF P0.22 P0.09/TRACEDATA2 P0.11/TRACEDATA0 P0.12/TRACECLK P0.13/QSPI0 P0.14/QSPI1 P0.20 P0.21 P0.23 P0.24 P0.25/AIN4 P0.05/AIN1 P0.06/AIN2 P0.07/AIN3 C7 1.0 µ F VDD_nRF C5 1.0 µ F P0.15/QSPI2 P0.02/NFC1 P0.26/AIN5 P0.27/AIN6 C17 4.7 µ F VBUS C18 4.7 µ F P1.00 P1.01 P1.02/I2C P1.03/I2C P1.04 P1.05 P1.06 P1.07 P1.08 P1.09 D_N D_P P0.28/AIN7 P0.30 P0.31 P0.29 RESET P0.10/TRACEDATA1 C10 100nF C11 100nF C12 100nF VDD_nRF VDD AJ31 DECRF G31 VDD N31 VDD AL11 DCC A21 DCCH J1 VBUS A5 DECUSB B6 VDD AL25 DECR A27 DCCD B10 DECD A15 VDD AL17 DECA A13 DECN A23 nRF5340 VDD L1 VDDH E1 VDD U1 VDD C1 VDD E31 VDD AL7 VDD AL3 VDD AC1 VDD A19 VDD B8 VDD AG1 VDD B28 ANT L31 XC1 C31 XC2 B30 SWDCLK W31 SWDIO AA31 D- B4 D+ B2 RESET AC31 U1A nRF5340-QKAA P0.00/XL1 N1 P0.01/XL2 R1 P0.26/AIN5 AL29 P0.27/AIN6 AK30 P0.06/AIN2 AB2 P0.08/TRACEDATA[3] AH2 P0.16/QSPI[3] AL9 P0.02/NFC1 W1 P0.20 AK16 P0.04/AIN0 V2 P0.05/AIN1 Y2 P0.22 AK18 P0.23 AK20 P0.24 AL27 P0.25/AIN4 AK28 P0.19 AL13 P0.17/QSPI_CLK AK12 P0.03/NFC2 AA1 P0.18/QSPI_CS AK14 P0.07/AIN3 AD2 P0.09/TRACEDATA[2] AJ1 P0.11/TRACEDATA[0] AK4 P0.12/TRACECLK AK6 P0.13/QSPI[0] AL5 P0.14/QSPI[1] AK8 P0.15/QSPI[2] AK10 P0.21 AL15 P0.28/AIN7 AE31 P0.30 B24 P0.31 B22 P0.29 U31 P0.10/TRACEDATA[1] AK2 U1B nRF5340-QKAA P1.11 B20 P1.10 R31 P1.09 AK26 P1.01 P2 P1.02/I2C AE1 P1.03/I2C AF2 P1.06 AL21 P1.07 AK24 P1.08 AL23 P1.12 B18 P1.13 A17 P1.14 B16 P1.15 B14 P1.00 M2 P1.05 AK22 P1.04 AL19 U1C nRF5340-QKAA P1.10 P1.11 P1.12 P1.13 P1.14 P1.15 C13 100nF C14 100nF C15 100nF C21 N.C. L1 2.2nH ANT R1 2R2 N.C. G1 N.C. B26 VSS_PAD 104 N.C. H2 N.C. B12 N.C. A25 N.C. J31 N.C. D2 N.C. F2 N.C. T2 N.C. AG31 N.C. A1 N.C. A31 N.C. AL1 N.C. AL31 U1D nRF5340-QKAA
Note: For PCB reference layouts, see the product page for the nRF5340 on www.nordicsemi.com.
Table 11. Bill of material for circuit configuration no. 4
Designator Value Description Footprint
C1 0.7 pF Capacitor, NP0, ±0.05 pF 0201
C2, C3, C5, C7 1.0 µF Capacitor, X7S, ±10% 0402
C4 2.2 nF Capacitor, X7R, ±10% 0201
C6, C8, C9, C10, C11, C12, C13, C14, C15 100 nF Capacitor, X7S, ±10% 0201
C17 4.7 µF Capacitor, X7S, ±10% 0603
C18 4.7 µF Capacitor, X7R, ±10% 0603
C19 2.2 µF Capacitor, X7R, ±10% 0603
C21 N.C. Not mounted 0201
L1 2.2 nH High frequency chip inductor, ±5% 0201
R1 2.2 Ω Resistor, ±1%, 0.05 W 0201
U1 nRF5340-QKAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4GHz proprietary System on Chip AQFN-94
X1 32 MHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: ±30 ppm. For frequency tolerance requirements, see 32 MHz crystal oscillator (HFXO). XTAL_2016
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

Circuit configuration no. 1 for CLAA WLCSP

Circuit configuration number 1 for CLAA WLCSP is showing the schematic and the bill of materials table.

Table 12. Configuration summary for circuit configuration no. 1
Config no. Supply configuration Enabled features
VDDH VDD EXTSUPPLY DCDC on VREGH DCDC on VREGMAIN and VREGRADIO USB NFC
Config. 1 Battery/Ext. regulator N/A Yes Yes Yes Yes No
Figure 5. Circuit configuration no. 1 schematic

image/svg+xml XC1 XC2 VDD_nRF RF P0.00/XL1 P0.01/XL2 X1 32MHz C4 2.2nF C2 1.0 µ F C6 100nF P0.19 P0.16/QSPI3 P0.17/QSPI_CLK L3 10 µ H C3 1.0 µ F C1 0.7pF P0.03/NFC2 P0.04/AIN0 VDD_nRF P0.18/QSPI_CS X2 32.768kHz L5 10 µ H VDD_HV C8 100nF C17 1.0 µ F P0.08/TRACEDATA3 C9 100nF P0.22 C18 4.7 µ F P0.09/TRACEDATA2 P0.11/TRACEDATA0 P0.12/TRACECLK P0.13/QSPI0 P0.14/QSPI1 P0.20 P0.21 P0.23 P0.24 P0.25/AIN4 P0.05/AIN1 P0.06/AIN2 P0.07/AIN3 L4 10 µ H C7 1.0 µ F C14 1.0 µ F VDD_nRF C5 1.0 µ F P0.15/QSPI2 P0.02/NFC1 P0.26/AIN5 P0.27/AIN6 C15 4.7 µ F VBUS C16 4.7 µ F P1.00 P1.01 P1.02/I2C P1.03/I2C P1.04 P1.05 P1.06 P1.07 P1.08 P1.09 P0.28/AIN7 P0.30 P0.31 P0.29 P0.10/TRACEDATA1 C10 1.0 µ F C12 100nF VDD_nRF DECRF B1 VDD H11 VDD L5 DCC B6 DCCH D11 VBUS B11 DECUSB C11 VDD K1 DECR B4 DCCD A9 DECD A7 DECA B8 DECN B5 nRF5340 VDD E11 VDDH B12 VDD D2 VDD B7 VDD B10 VDD L11 VDD A3 ANT D1 XC1 A1 XC2 A2 SWDCLK F2 SWDIO F1 D- A11 D+ A12 RESET G2 U1A nRF5340-CLAA P0.00/XL1 F11 P0.01/XL2 F12 P0.26/AIN5 J2 P0.27/AIN6 H1 P0.06/AIN2 H10 P0.08/TRACEDATA[3] L12 P0.16/QSPI[3] K8 P0.02/NFC1 G11 P0.20 K5 P0.04/AIN0 G10 P0.05/AIN1 F10 P0.22 K4 P0.23 H3 P0.24 K2 P0.25/AIN4 L1 P0.19 J5 P0.17/QSPI_CLK L7 P0.03/NFC2 H12 P0.18/QSPI_CS K7 P0.07/AIN3 J10 P0.09/TRACEDATA[2] J9 P0.11/TRACEDATA[0] J7 P0.12/TRACECLK J6 P0.13/QSPI[0] K10 P0.14/QSPI[1] K9 P0.15/QSPI[2] L9 P0.21 J4 P0.28/AIN7 E3 P0.30 C4 P0.31 C5 P0.29 E2 P0.10/TRACEDATA[1] J8 U1B nRF5340-CLAA P1.11 C6 P1.10 E4 P1.09 H2 P1.01 E10 P1.02/I2C J11 P1.03/I2C K12 P1.06 J3 P1.07 G3 P1.08 F3 P1.12 C7 P1.13 C8 P1.14 C9 P1.15 C10 P1.00 D10 P1.05 L3 P1.04 K3 U1C nRF5340-CLAA P1.10 P1.11 P1.12 P1.13 P1.14 P1.15 C13 100nF L2 2.2nH C19 N.C. C11 100nF L1 2.2nH ANT VSS C2 VSS B9 VSS K11 VSS K6 VSS E6 VSS D12 VSS B2 VSS A5 VSS E5 VSS E7 VSS E8 VSS F5 VSS F6 VSS F7 VSS F8 VSS G5 VSS G6 VSS G7 VSS G8 U1D nRF5340-CLAA SWDCLK SWDIO D_N D_P RESET Optional R1 2R2
Note: For PCB reference layouts, see the product page for the nRF5340 on www.nordicsemi.com.
Table 13. Bill of material for circuit configuration no. 1
Designator Value Description Footprint
C1 0.7 pF Capacitor, NP0, ±0.05 pF 0201
C2, C3, C5, C7, C10, C14, C17 1.0 µF Capacitor, X7S, ±10% 0402
C4 2.2 nF Capacitor, X7R, ±10% 0201
C6, C8, C9, C11, C12, C13 100 nF Capacitor, X7S, ±10% 0201
C15, C18 4.7 µF Capacitor, X7S, ±10% 0603
C16 4.7 µF Capacitor, X7R, ±10% 0603
C19 N.C. Not mounted 0201
L1, L2 2.2 nH High frequency chip inductor, ±5% 0201
L3, L4 10 µH Inductor, 50 mA, ±20% 0603
L5 10 µH Inductor, 80 mA, ±20% 0603
R1 2.2 Ω Resistor, ±1%, 0.05 W 0201
U1 nRF5340-CLAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4GHz proprietary System on Chip WLCSP-95
X1 32 MHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: ±30 ppm. For frequency tolerance requirements, see 32 MHz crystal oscillator (HFXO). XTAL_2016
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

Circuit configuration no. 2 for CLAA WLCSP

Circuit configuration number 2 for CLAA WLCSP is showing the schematic and the bill of materials table.

Table 14. Configuration summary for circuit configuration no. 2
Config no. Supply configuration Enabled features
VDDH VDD EXTSUPPLY DCDC on VREGH DCDC on VREGMAIN and VREGRADIO USB NFC
Config. 2 N/A Battery/Ext. regulator No No Yes Yes Yes
Figure 6. Circuit configuration no. 2 schematic

image/svg+xml XC1 XC2 VDD_nRF RF P0.00/XL1 P0.01/XL2 X1 32MHz C4 2.2nF C2 1.0 µ F C6 100nF P0.19 P0.16/QSPI3 P0.17/QSPI_CLK L3 10 µ H C3 1.0 µ F C1 0.7pF P0.03/NFC2 P0.04/AIN0 VDD_nRF P0.18/QSPI_CS X2 32.768kHz C8 100nF P0.08/TRACEDATA3 C9 100nF P0.22 P0.09/TRACEDATA2 P0.11/TRACEDATA0 P0.12/TRACECLK P0.13/QSPI0 P0.14/QSPI1 P0.20 P0.21 P0.23 P0.24 P0.25/AIN4 P0.05/AIN1 P0.06/AIN2 P0.07/AIN3 L4 10 µ H C7 1.0 µ F C14 1.0 µ F VDD_nRF C5 1.0 µ F P0.15/QSPI2 P0.02/NFC1 P0.26/AIN5 P0.27/AIN6 C15 4.7 µ F VBUS C16 4.7 µ F P1.00 P1.01 P1.02/I2C P1.03/I2C P1.04 P1.05 P1.06 P1.07 P1.08 P1.09 P0.28/AIN7 P0.30 P0.31 P0.29 P0.10/TRACEDATA1 C10 1.0 µ F C12 100nF VDD_nRF DECRF B1 VDD H11 VDD L5 DCC B6 DCCH D11 VBUS B11 DECUSB C11 VDD K1 DECR B4 DCCD A9 DECD A7 DECA B8 DECN B5 nRF5340 VDD E11 VDDH B12 VDD D2 VDD B7 VDD B10 VDD L11 VDD A3 ANT D1 XC1 A1 XC2 A2 SWDCLK F2 SWDIO F1 D- A11 D+ A12 RESET G2 U1A nRF5340-CLAA P0.00/XL1 F11 P0.01/XL2 F12 P0.26/AIN5 J2 P0.27/AIN6 H1 P0.06/AIN2 H10 P0.08/TRACEDATA[3] L12 P0.16/QSPI[3] K8 P0.02/NFC1 G11 P0.20 K5 P0.04/AIN0 G10 P0.05/AIN1 F10 P0.22 K4 P0.23 H3 P0.24 K2 P0.25/AIN4 L1 P0.19 J5 P0.17/QSPI_CLK L7 P0.03/NFC2 H12 P0.18/QSPI_CS K7 P0.07/AIN3 J10 P0.09/TRACEDATA[2] J9 P0.11/TRACEDATA[0] J7 P0.12/TRACECLK J6 P0.13/QSPI[0] K10 P0.14/QSPI[1] K9 P0.15/QSPI[2] L9 P0.21 J4 P0.28/AIN7 E3 P0.30 C4 P0.31 C5 P0.29 E2 P0.10/TRACEDATA[1] J8 U1B nRF5340-CLAA P1.11 C6 P1.10 E4 P1.09 H2 P1.01 E10 P1.02/I2C J11 P1.03/I2C K12 P1.06 J3 P1.07 G3 P1.08 F3 P1.12 C7 P1.13 C8 P1.14 C9 P1.15 C10 P1.00 D10 P1.05 L3 P1.04 K3 U1C nRF5340-CLAA P1.10 P1.11 P1.12 P1.13 P1.14 P1.15 C13 100nF L2 2.2nH C19 N.C. C11 100nF L1 2.2nH ANT VSS C2 VSS B9 VSS K11 VSS K6 VSS E6 VSS D12 VSS B2 VSS A5 VSS E5 VSS E7 VSS E8 VSS F5 VSS F6 VSS F7 VSS F8 VSS G5 VSS G6 VSS G7 VSS G8 U1D nRF5340-CLAA SWDCLK SWDIO D_N D_P RESET Optional CT1 CT3 Note: The value of CT1, CT2, CT3 and CT4 must be tuned to match the selected NFC antenna. CT2 CT4 R1 2R2
Note: For PCB reference layouts, see the product page for the nRF5340 on www.nordicsemi.com.
Table 15. Bill of material for circuit configuration no. 2
Designator Value Description Footprint
C1 0.7 pF Capacitor, NP0, ±0.05 pF 0201
C2, C3, C5, C7, C10, C14 1.0 µF Capacitor, X7S, ±10% 0402
C4 2.2 nF Capacitor, X7R, ±10% 0201
C6, C8, C9, C11, C12, C13 100 nF Capacitor, X7S, ±10% 0201
C15 4.7 µF Capacitor, X7S, ±10% 0603
C16 4.7 µF Capacitor, X7R, ±10% 0603
C19 N.C. Not mounted 0201
CT1, CT2, CT3, CT4 Antenna dependent Capacitor, NP0, ±5% 0201
L1, L2 2.2 nH High frequency chip inductor, ±5% 0201
L3, L4 10 µH Inductor, 50 mA, ±20% 0603
R1 2.2 Ω Resistor, ±1%, 0.05 W 0201
U1 nRF5340-CLAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4GHz proprietary System on Chip WLCSP-95
X1 32 MHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: ±30 ppm. For frequency tolerance requirements, see 32 MHz crystal oscillator (HFXO). XTAL_2016
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

Circuit configuration no. 3 for CLAA WLCSP

Circuit configuration number 3 for CLAA WLCSP is showing the schematic and the bill of materials table.

Table 16. Configuration summary for circuit configuration no. 3
Config no. Supply configuration Enabled features
VDDH VDD EXTSUPPLY DCDC on VREGH DCDC on VREGMAIN and VREGRADIO USB NFC
Config. 3 N/A Battery/Ext. regulator No No Yes No No
Figure 7. Circuit configuration no. 3 schematic

image/svg+xml XC1 XC2 VDD_nRF RF P0.00/XL1 P0.01/XL2 X1 32MHz C4 2.2nF C2 1.0 µ F C6 100nF P0.19 P0.16/QSPI3 P0.17/QSPI_CLK L3 10 µ H C3 1.0 µ F C1 0.7pF P0.03/NFC2 P0.04/AIN0 VDD_nRF P0.18/QSPI_CS X2 32.768kHz C8 100nF P0.08/TRACEDATA3 C9 100nF P0.22 P0.09/TRACEDATA2 P0.11/TRACEDATA0 P0.12/TRACECLK P0.13/QSPI0 P0.14/QSPI1 P0.20 P0.21 P0.23 P0.24 P0.25/AIN4 P0.05/AIN1 P0.06/AIN2 P0.07/AIN3 L4 10 µ H C7 1.0 µ F C14 1.0 µ F VDD_nRF C5 1.0 µ F P0.15/QSPI2 P0.02/NFC1 P0.26/AIN5 P0.27/AIN6 P1.00 P1.01 P1.02/I2C P1.03/I2C P1.04 P1.05 P1.06 P1.07 P1.08 P1.09 P0.28/AIN7 P0.30 P0.31 P0.29 P0.10/TRACEDATA1 C10 1.0 µ F C12 100nF VDD_nRF DECRF B1 VDD H11 VDD L5 DCC B6 DCCH D11 VBUS B11 DECUSB C11 VDD K1 DECR B4 DCCD A9 DECD A7 DECA B8 DECN B5 nRF5340 VDD E11 VDDH B12 VDD D2 VDD B7 VDD B10 VDD L11 VDD A3 ANT D1 XC1 A1 XC2 A2 SWDCLK F2 SWDIO F1 D- A11 D+ A12 RESET G2 U1A nRF5340-CLAA P0.00/XL1 F11 P0.01/XL2 F12 P0.26/AIN5 J2 P0.27/AIN6 H1 P0.06/AIN2 H10 P0.08/TRACEDATA[3] L12 P0.16/QSPI[3] K8 P0.02/NFC1 G11 P0.20 K5 P0.04/AIN0 G10 P0.05/AIN1 F10 P0.22 K4 P0.23 H3 P0.24 K2 P0.25/AIN4 L1 P0.19 J5 P0.17/QSPI_CLK L7 P0.03/NFC2 H12 P0.18/QSPI_CS K7 P0.07/AIN3 J10 P0.09/TRACEDATA[2] J9 P0.11/TRACEDATA[0] J7 P0.12/TRACECLK J6 P0.13/QSPI[0] K10 P0.14/QSPI[1] K9 P0.15/QSPI[2] L9 P0.21 J4 P0.28/AIN7 E3 P0.30 C4 P0.31 C5 P0.29 E2 P0.10/TRACEDATA[1] J8 U1B nRF5340-CLAA P1.11 C6 P1.10 E4 P1.09 H2 P1.01 E10 P1.02/I2C J11 P1.03/I2C K12 P1.06 J3 P1.07 G3 P1.08 F3 P1.12 C7 P1.13 C8 P1.14 C9 P1.15 C10 P1.00 D10 P1.05 L3 P1.04 K3 U1C nRF5340-CLAA P1.10 P1.11 P1.12 P1.13 P1.14 P1.15 C13 100nF L2 2.2nH C19 N.C. C11 100nF L1 2.2nH ANT VSS C2 VSS B9 VSS K11 VSS K6 VSS E6 VSS D12 VSS B2 VSS A5 VSS E5 VSS E7 VSS E8 VSS F5 VSS F6 VSS F7 VSS F8 VSS G5 VSS G6 VSS G7 VSS G8 U1D nRF5340-CLAA SWDCLK SWDIO RESET Optional
Note: For PCB reference layouts, see the product page for the nRF5340 on www.nordicsemi.com.
Table 17. Bill of material for circuit configuration no. 3
Designator Value Description Footprint
C1 0.7 pF Capacitor, NP0, ±0.05 pF 0201
C2, C3, C5, C7, C10, C14 1.0 µF Capacitor, X7S, ±10% 0402
C4 2.2 nF Capacitor, X7R, ±10% 0201
C6, C8, C9, C11, C12, C13 100 nF Capacitor, X7S, ±10% 0201
C19 N.C. Not mounted 0201
L1, L2 2.2 nH High frequency chip inductor, ±5% 0201
L3, L4 10 µH Inductor, 50 mA, ±20% 0603
U1 nRF5340-CLAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4GHz proprietary System on Chip WLCSP-95
X1 32 MHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: ±30 ppm. For frequency tolerance requirements, see 32 MHz crystal oscillator (HFXO). XTAL_2016
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

Circuit configuration no. 4 for CLAA WLCSP

Circuit configuration number 4 for CLAA WLCSP is showing the schematic and the bill of materials table.

Table 18. Configuration summary for circuit configuration no. 4
Config no. Supply configuration Enabled features
VDDH VDD EXTSUPPLY DCDC on VREGH DCDC on VREGMAIN and VREGRADIO USB NFC
Config. 4 USB (VDDH = VBUS) N/A No No No Yes No
Figure 8. Circuit configuration no. 4 schematic

image/svg+xml XC1 XC2 VDD_nRF RF P0.00/XL1 P0.01/XL2 X1 32MHz C4 2.2nF C2 1.0 µ F C6 100nF P0.19 P0.16/QSPI3 P0.17/QSPI_CLK C3 1.0 µ F C1 0.7pF P0.03/NFC2 P0.04/AIN0 VDD_nRF P0.18/QSPI_CS X2 32.768kHz C8 100nF C17 1.0 µ F P0.08/TRACEDATA3 C9 100nF P0.22 P0.09/TRACEDATA2 P0.11/TRACEDATA0 P0.12/TRACECLK P0.13/QSPI0 P0.14/QSPI1 P0.20 P0.21 P0.23 P0.24 P0.25/AIN4 P0.05/AIN1 P0.06/AIN2 P0.07/AIN3 C7 1.0 µ F VDD_nRF C5 1.0 µ F P0.15/QSPI2 P0.02/NFC1 P0.26/AIN5 P0.27/AIN6 C15 4.7 µ F VBUS C16 4.7 µ F P1.00 P1.01 P1.02/I2C P1.03/I2C P1.04 P1.05 P1.06 P1.07 P1.08 P1.09 P0.28/AIN7 P0.30 P0.31 P0.29 P0.10/TRACEDATA1 C10 1.0 µ F C12 100nF VDD_nRF DECRF B1 VDD H11 VDD L5 DCC B6 DCCH D11 VBUS B11 DECUSB C11 VDD K1 DECR B4 DCCD A9 DECD A7 DECA B8 DECN B5 nRF5340 VDD E11 VDDH B12 VDD D2 VDD B7 VDD B10 VDD L11 VDD A3 ANT D1 XC1 A1 XC2 A2 SWDCLK F2 SWDIO F1 D- A11 D+ A12 RESET G2 U1A nRF5340-CLAA P0.00/XL1 F11 P0.01/XL2 F12 P0.26/AIN5 J2 P0.27/AIN6 H1 P0.06/AIN2 H10 P0.08/TRACEDATA[3] L12 P0.16/QSPI[3] K8 P0.02/NFC1 G11 P0.20 K5 P0.04/AIN0 G10 P0.05/AIN1 F10 P0.22 K4 P0.23 H3 P0.24 K2 P0.25/AIN4 L1 P0.19 J5 P0.17/QSPI_CLK L7 P0.03/NFC2 H12 P0.18/QSPI_CS K7 P0.07/AIN3 J10 P0.09/TRACEDATA[2] J9 P0.11/TRACEDATA[0] J7 P0.12/TRACECLK J6 P0.13/QSPI[0] K10 P0.14/QSPI[1] K9 P0.15/QSPI[2] L9 P0.21 J4 P0.28/AIN7 E3 P0.30 C4 P0.31 C5 P0.29 E2 P0.10/TRACEDATA[1] J8 U1B nRF5340-CLAA P1.11 C6 P1.10 E4 P1.09 H2 P1.01 E10 P1.02/I2C J11 P1.03/I2C K12 P1.06 J3 P1.07 G3 P1.08 F3 P1.12 C7 P1.13 C8 P1.14 C9 P1.15 C10 P1.00 D10 P1.05 L3 P1.04 K3 U1C nRF5340-CLAA P1.10 P1.11 P1.12 P1.13 P1.14 P1.15 C13 100nF L2 2.2nH C19 N.C. C11 100nF L1 2.2nH ANT VSS C2 VSS B9 VSS K11 VSS K6 VSS E6 VSS D12 VSS B2 VSS A5 VSS E5 VSS E7 VSS E8 VSS F5 VSS F6 VSS F7 VSS F8 VSS G5 VSS G6 VSS G7 VSS G8 U1D nRF5340-CLAA SWDCLK SWDIO D_N D_P RESET Optional R1 2R2
Note: For PCB reference layouts, see the product page for the nRF5340 on www.nordicsemi.com.
Table 19. Bill of material for circuit configuration no. 4
Designator Value Description Footprint
C1 0.7 pF Capacitor, NP0, ±0.05 pF 0201
C2, C3, C5, C7, C10, C17 1.0 µF Capacitor, X7S, ±10% 0402
C4 2.2 nF Capacitor, X7R, ±10% 0201
C6, C8, C9, C11, C12, C13 100 nF Capacitor, X7S, ±10% 0201
C15 4.7 µF Capacitor, X7S, ±10% 0603
C16 4.7 µF Capacitor, X7R, ±10% 0603
C19 N.C. Not mounted 0201
L1, L2 2.2 nH High frequency chip inductor, ±5% 0201
R1 2.2 Ω Resistor, ±1%, 0.05 W 0201
U1 nRF5340-CLAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4GHz proprietary System on Chip WLCSP-95
X1 32 MHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: ±30 ppm. For frequency tolerance requirements, see 32 MHz crystal oscillator (HFXO). XTAL_2016
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

Circuit configuration no. 1 for CMAA WLCSP

Circuit configuration number 1 for CMAA WLCSP is showing the schematic and the bill of materials table.

Table 20. Configuration summary for circuit configuration no. 1
Config no. Supply configuration Enabled features
VDDH VDD EXTSUPPLY DCDC on VREGH DCDC on VREGMAIN and VREGRADIO USB NFC
Config. 1 Battery/Ext. regulator N/A Yes Yes Yes Yes No
Figure 9. Circuit configuration no. 1 schematic

XC1 XC2 VDD_nRF RF P0.00/XL1 P0.01/XL2 X1 32MHz C4 2.2nF C2 1.0µF C6 100nF P0.19 P0.16/QSPI3 P0.17/QSPI_CLK L3 10µH C3 1.0µF C1 0.7pF P0.03/NFC2 P0.04/AIN0 VDD_nRF P0.18/QSPI_CS X2 32.768kHz L5 10µH VDD_HV C8 100nF C17 1.0µF P0.08/TRACEDATA3 C9 100nF P0.22 C18 4.7µF P0.09/TRACEDATA2 P0.11/TRACEDATA0 P0.12/TRACECLK P0.13/QSPI0 P0.14/QSPI1 P0.20 P0.21 P0.23 P0.24 P0.25/AIN4 P0.05/AIN1 P0.06/AIN2 P0.07/AIN3 L4 10µH C7 1.0µF C14 1.0µF VDD_nRF C5 1.0µF P0.15/QSPI2 P0.02/NFC1 P0.26/AIN5 P0.27/AIN6 C15 4.7µF VBUS C16 4.7µF P1.00 P1.01 P1.02/TWI P1.03/TWI P1.04 P1.05 P1.06 P1.07 P1.08 P1.09 P0.28/AIN7 P0.30 P0.31 P0.29 P0.10/TRACEDATA1 C10 1.0µF C12 100nF VDD_nRF DECRF B1 VDD H11 VDD L5 DCC B6 DCCH D11 VBUS B11 DECUSB C11 VDD K1 DECR B4 DCCD A9 DECD A7 DECA B8 DECN B5 VDD E11 VDDH B12 VDD D2 VDD B7 VDD B10 VDD L11 VDD A3 ANT D1 XC1 A1 XC2 A2 SWDCLK F2 SWDIO F1 D- A11 D+ A12 RESET G2 U1A nRF5340-CMAA P0.00/XL1 F11 P0.01/XL2 F12 P0.26/AIN5 J2 P0.27/AIN6 H1 P0.06/AIN2 H10 P0.08/TRACEDATA[3] L12 P0.16/QSPI[3] K8 P0.02/NFC1 G11 P0.20 K5 P0.04/AIN0 G10 P0.05/AIN1 F10 P0.22 K4 P0.23 H3 P0.24 K2 P0.25/AIN4 L1 P0.19 J5 P0.17/QSPI_CLK L7 P0.03/NFC2 H12 P0.18/QSPI_CS K7 P0.07/AIN3 J10 P0.09/TRACEDATA[2] J9 P0.11/TRACEDATA[0] J7 P0.12/TRACECLK J6 P0.13/QSPI[0] K10 P0.14/QSPI[1] K9 P0.15/QSPI[2] L9 P0.21 J4 P0.28/AIN7 E3 P0.30 C4 P0.31 C5 P0.29 E2 P0.10/TRACEDATA[1] J8 U1B nRF5340-CMAA P1.11 C6 P1.10 E4 P1.09 H2 P1.01 E10 P1.02/TWI J11 P1.03/TWI K12 P1.06 J3 P1.07 G3 P1.08 F3 P1.12 C7 P1.13 C8 P1.14 C9 P1.15 C10 P1.00 D10 P1.05 L3 P1.04 K3 U1C nRF5340-CMAA P1.10 P1.11 P1.12 P1.13 P1.14 P1.15 C13 100nF L2 2.2nH C19 N.C. C11 100nF L1 2.2nH ANT VSS C2 VSS B9 VSS K11 VSS K6 VSS E6 VSS D12 VSS B2 VSS A5 VSS E5 VSS E7 VSS E8 VSS F5 VSS F6 VSS F7 VSS F8 VSS G5 VSS G6 VSS G7 VSS G8 U1D nRF5340-CMAA SWDCLK SWDIO D_N D_P RESET Optional R1 2R2
Note: For PCB reference layouts, see the product page for the nRF5340 on www.nordicsemi.com.
Table 21. Bill of material for circuit configuration no. 1
Designator Value Description Footprint
C1 0.7 pF Capacitor, NP0, ±0.05 pF 0201
C2, C3, C5, C7, C10, C14, C17 1.0 µF Capacitor, X7S, ±10% 0402
C4 2.2 nF Capacitor, X7R, ±10% 0201
C6, C8, C9, C11, C12, C13 100 nF Capacitor, X7S, ±10% 0201
C15, C18 4.7 µF Capacitor, X7S, ±10% 0603
C16 4.7 µF Capacitor, X7R, ±10% 0603
C19 N.C. Not mounted 0201
L1, L2 2.2 nH High frequency chip inductor, ±5% 0201
L3, L4 10 µH Inductor, 50 mA, ±20% 0603
L5 10 µH Inductor, 80 mA, ±20% 0603
R1 2.2 Ω Resistor, ±1%, 0.05 W 0201
U1 nRF5340-CMAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4GHz proprietary System on Chip WLCSP-95
X1 32 MHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: ±30 ppm. For frequency tolerance requirements, see 32 MHz crystal oscillator (HFXO). XTAL_2016
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

Circuit configuration no. 2 for CMAA WLCSP

Circuit configuration number 2 for CMAA WLCSP is showing the schematic and the bill of materials table.

Table 22. Configuration summary for circuit configuration no. 2
Config no. Supply configuration Enabled features
VDDH VDD EXTSUPPLY DCDC on VREGH DCDC on VREGMAIN and VREGRADIO USB NFC
Config. 2 N/A Battery/Ext. regulator No No Yes Yes Yes
Figure 10. Circuit configuration no. 2 schematic

XC1 XC2 VDD_nRF RF P0.00/XL1 P0.01/XL2 X1 32MHz C4 2.2nF C2 1.0µF C6 100nF P0.19 P0.16/QSPI3 P0.17/QSPI_CLK L3 10µH C3 1.0µF C1 0.7pF P0.03/NFC2 P0.04/AIN0 VDD_nRF P0.18/QSPI_CS X2 32.768kHz C8 100nF P0.08/TRACEDATA3 C9 100nF P0.22 P0.09/TRACEDATA2 P0.11/TRACEDATA0 P0.12/TRACECLK P0.13/QSPI0 P0.14/QSPI1 P0.20 P0.21 P0.23 P0.24 P0.25/AIN4 P0.05/AIN1 P0.06/AIN2 P0.07/AIN3 L4 10µH C7 1.0µF C14 1.0µF VDD_nRF C5 1.0µF P0.15/QSPI2 P0.02/NFC1 P0.26/AIN5 P0.27/AIN6 C15 4.7µF VBUS C16 4.7µF P1.00 P1.01 P1.02/TWI P1.03/TWI P1.04 P1.05 P1.06 P1.07 P1.08 P1.09 P0.28/AIN7 P0.30 P0.31 P0.29 P0.10/TRACEDATA1 C10 1.0µF C12 100nF VDD_nRF DECRF B1 VDD H11 VDD L5 DCC B6 DCCH D11 VBUS B11 DECUSB C11 VDD K1 DECR B4 DCCD A9 DECD A7 DECA B8 DECN B5 VDD E11 VDDH B12 VDD D2 VDD B7 VDD B10 VDD L11 VDD A3 ANT D1 XC1 A1 XC2 A2 SWDCLK F2 SWDIO F1 D- A11 D+ A12 RESET G2 U1A nRF5340-CMAA P0.00/XL1 F11 P0.01/XL2 F12 P0.26/AIN5 J2 P0.27/AIN6 H1 P0.06/AIN2 H10 P0.08/TRACEDATA[3] L12 P0.16/QSPI[3] K8 P0.02/NFC1 G11 P0.20 K5 P0.04/AIN0 G10 P0.05/AIN1 F10 P0.22 K4 P0.23 H3 P0.24 K2 P0.25/AIN4 L1 P0.19 J5 P0.17/QSPI_CLK L7 P0.03/NFC2 H12 P0.18/QSPI_CS K7 P0.07/AIN3 J10 P0.09/TRACEDATA[2] J9 P0.11/TRACEDATA[0] J7 P0.12/TRACECLK J6 P0.13/QSPI[0] K10 P0.14/QSPI[1] K9 P0.15/QSPI[2] L9 P0.21 J4 P0.28/AIN7 E3 P0.30 C4 P0.31 C5 P0.29 E2 P0.10/TRACEDATA[1] J8 U1B nRF5340-CMAA P1.11 C6 P1.10 E4 P1.09 H2 P1.01 E10 P1.02/TWI J11 P1.03/TWI K12 P1.06 J3 P1.07 G3 P1.08 F3 P1.12 C7 P1.13 C8 P1.14 C9 P1.15 C10 P1.00 D10 P1.05 L3 P1.04 K3 U1C nRF5340-CMAA P1.10 P1.11 P1.12 P1.13 P1.14 P1.15 C13 100nF L2 2.2nH C19 N.C. C11 100nF L1 2.2nH ANT VSS C2 VSS B9 VSS K11 VSS K6 VSS E6 VSS D12 VSS B2 VSS A5 VSS E5 VSS E7 VSS E8 VSS F5 VSS F6 VSS F7 VSS F8 VSS G5 VSS G6 VSS G7 VSS G8 U1D nRF5340-CMAA SWDCLK SWDIO D_N D_P RESET Optional CT1 CT3 Note: The value of CT1, CT2, CT3 and CT4 must be tuned to match the selected NFC antenna. CT2 CT4 R1 2R2
Note: For PCB reference layouts, see the product page for the nRF5340 on www.nordicsemi.com.
Table 23. Bill of material for circuit configuration no. 2
Designator Value Description Footprint
C1 0.7 pF Capacitor, NP0, ±0.05 pF 0201
C2, C3, C5, C7, C10, C14 1.0 µF Capacitor, X7S, ±10% 0402
C4 2.2 nF Capacitor, X7R, ±10% 0201
C6, C8, C9, C11, C12, C13 100 nF Capacitor, X7S, ±10% 0201
C15 4.7 µF Capacitor, X7S, ±10% 0603
C16 4.7 µF Capacitor, X7R, ±10% 0603
C19 N.C. Not mounted 0201
CT1, CT2, CT3, CT4 Antenna dependent Capacitor, NP0, ±5% 0201
L1, L2 2.2 nH High frequency chip inductor, ±5% 0201
L3, L4 10 µH Inductor, 50 mA, ±20% 0603
R1 2.2 Ω Resistor, ±1%, 0.05 W 0201
U1 nRF5340-CMAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4GHz proprietary System on Chip WLCSP-95
X1 32 MHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: ±30 ppm. For frequency tolerance requirements, see 32 MHz crystal oscillator (HFXO). XTAL_2016
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

Circuit configuration no. 3 for CMAA WLCSP

Circuit configuration number 3 for CMAA WLCSP is showing the schematic and the bill of materials table.

Table 24. Configuration summary for circuit configuration no. 3
Config no. Supply configuration Enabled features
VDDH VDD EXTSUPPLY DCDC on VREGH DCDC on VREGMAIN and VREGRADIO USB NFC
Config. 3 N/A Battery/Ext. regulator No No Yes No No
Figure 11. Circuit configuration no. 3 schematic

XC1 XC2 VDD_nRF RF P0.00/XL1 P0.01/XL2 X1 32MHz C4 2.2nF C2 1.0µF C6 100nF P0.19 P0.16/QSPI3 P0.17/QSPI_CLK L3 10µH C3 1.0µF C1 0.7pF P0.03/NFC2 P0.04/AIN0 VDD_nRF P0.18/QSPI_CS X2 32.768kHz C8 100nF P0.08/TRACEDATA3 C9 100nF P0.22 P0.09/TRACEDATA2 P0.11/TRACEDATA0 P0.12/TRACECLK P0.13/QSPI0 P0.14/QSPI1 P0.20 P0.21 P0.23 P0.24 P0.25/AIN4 P0.05/AIN1 P0.06/AIN2 P0.07/AIN3 L4 10µH C7 1.0µF C14 1.0µF VDD_nRF C5 1.0µF P0.15/QSPI2 P0.02/NFC1 P0.26/AIN5 P0.27/AIN6 P1.00 P1.01 P1.02/TWI P1.03/TWI P1.04 P1.05 P1.06 P1.07 P1.08 P1.09 P0.28/AIN7 P0.30 P0.31 P0.29 P0.10/TRACEDATA1 C10 1.0µF C12 100nF VDD_nRF DECRF B1 VDD H11 VDD L5 DCC B6 DCCH D11 VBUS B11 DECUSB C11 VDD K1 DECR B4 DCCD A9 DECD A7 DECA B8 DECN B5 VDD E11 VDDH B12 VDD D2 VDD B7 VDD B10 VDD L11 VDD A3 ANT D1 XC1 A1 XC2 A2 SWDCLK F2 SWDIO F1 D- A11 D+ A12 RESET G2 U1A nRF5340-CMAA P0.00/XL1 F11 P0.01/XL2 F12 P0.26/AIN5 J2 P0.27/AIN6 H1 P0.06/AIN2 H10 P0.08/TRACEDATA[3] L12 P0.16/QSPI[3] K8 P0.02/NFC1 G11 P0.20 K5 P0.04/AIN0 G10 P0.05/AIN1 F10 P0.22 K4 P0.23 H3 P0.24 K2 P0.25/AIN4 L1 P0.19 J5 P0.17/QSPI_CLK L7 P0.03/NFC2 H12 P0.18/QSPI_CS K7 P0.07/AIN3 J10 P0.09/TRACEDATA[2] J9 P0.11/TRACEDATA[0] J7 P0.12/TRACECLK J6 P0.13/QSPI[0] K10 P0.14/QSPI[1] K9 P0.15/QSPI[2] L9 P0.21 J4 P0.28/AIN7 E3 P0.30 C4 P0.31 C5 P0.29 E2 P0.10/TRACEDATA[1] J8 U1B nRF5340-CMAA P1.11 C6 P1.10 E4 P1.09 H2 P1.01 E10 P1.02/TWI J11 P1.03/TWI K12 P1.06 J3 P1.07 G3 P1.08 F3 P1.12 C7 P1.13 C8 P1.14 C9 P1.15 C10 P1.00 D10 P1.05 L3 P1.04 K3 U1C nRF5340-CMAA P1.10 P1.11 P1.12 P1.13 P1.14 P1.15 C13 100nF L2 2.2nH C19 N.C. C11 100nF L1 2.2nH ANT VSS C2 VSS B9 VSS K11 VSS K6 VSS E6 VSS D12 VSS B2 VSS A5 VSS E5 VSS E7 VSS E8 VSS F5 VSS F6 VSS F7 VSS F8 VSS G5 VSS G6 VSS G7 VSS G8 U1D nRF5340-CMAA SWDCLK SWDIO RESET Optional
Note: For PCB reference layouts, see the product page for the nRF5340 on www.nordicsemi.com.
Table 25. Bill of material for circuit configuration no. 3
Designator Value Description Footprint
C1 0.7 pF Capacitor, NP0, ±0.05 pF 0201
C2, C3, C5, C7, C10, C14 1.0 µF Capacitor, X7S, ±10% 0402
C4 2.2 nF Capacitor, X7R, ±10% 0201
C6, C8, C9, C11, C12, C13 100 nF Capacitor, X7S, ±10% 0201
C19 N.C. Not mounted 0201
L1, L2 2.2 nH High frequency chip inductor, ±5% 0201
L3, L4 10 µH Inductor, 50 mA, ±20% 0603
U1 nRF5340-CMAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4GHz proprietary System on Chip WLCSP-95
X1 32 MHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: ±30 ppm. For frequency tolerance requirements, see 32 MHz crystal oscillator (HFXO). XTAL_2016
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

Circuit configuration no. 4 for CMAA WLCSP

Circuit configuration number 4 for CMAA WLCSP is showing the schematic and the bill of materials table.

Table 26. Configuration summary for circuit configuration no. 4
Config no. Supply configuration Enabled features
VDDH VDD EXTSUPPLY DCDC on VREGH DCDC on VREGMAIN and VREGRADIO USB NFC
Config. 4 USB (VDDH = VBUS) N/A No No No Yes No
Figure 12. Circuit configuration no. 4 schematic

XC1 XC2 VDD_nRF RF P0.00/XL1 P0.01/XL2 X1 32MHz C4 2.2nF C2 1.0µF C6 100nF P0.19 P0.16/QSPI3 P0.17/QSPI_CLK C3 1.0µF C1 0.7pF P0.03/NFC2 P0.04/AIN0 VDD_nRF P0.18/QSPI_CS X2 32.768kHz C8 100nF C17 1.0µF P0.08/TRACEDATA3 C9 100nF P0.22 P0.09/TRACEDATA2 P0.11/TRACEDATA0 P0.12/TRACECLK P0.13/QSPI0 P0.14/QSPI1 P0.20 P0.21 P0.23 P0.24 P0.25/AIN4 P0.05/AIN1 P0.06/AIN2 P0.07/AIN3 C7 1.0µF VDD_nRF C5 1.0µF P0.15/QSPI2 P0.02/NFC1 P0.26/AIN5 P0.27/AIN6 C15 4.7µF VBUS C16 4.7µF P1.00 P1.01 P1.02/TWI P1.03/TWI P1.04 P1.05 P1.06 P1.07 P1.08 P1.09 P0.28/AIN7 P0.30 P0.31 P0.29 P0.10/TRACEDATA1 C10 1.0µF C12 100nF VDD_nRF DECRF B1 VDD H11 VDD L5 DCC B6 DCCH D11 VBUS B11 DECUSB C11 VDD K1 DECR B4 DCCD A9 DECD A7 DECA B8 DECN B5 VDD E11 VDDH B12 VDD D2 VDD B7 VDD B10 VDD L11 VDD A3 ANT D1 XC1 A1 XC2 A2 SWDCLK F2 SWDIO F1 D- A11 D+ A12 RESET G2 U1A nRF5340-CMAA P0.00/XL1 F11 P0.01/XL2 F12 P0.26/AIN5 J2 P0.27/AIN6 H1 P0.06/AIN2 H10 P0.08/TRACEDATA[3] L12 P0.16/QSPI[3] K8 P0.02/NFC1 G11 P0.20 K5 P0.04/AIN0 G10 P0.05/AIN1 F10 P0.22 K4 P0.23 H3 P0.24 K2 P0.25/AIN4 L1 P0.19 J5 P0.17/QSPI_CLK L7 P0.03/NFC2 H12 P0.18/QSPI_CS K7 P0.07/AIN3 J10 P0.09/TRACEDATA[2] J9 P0.11/TRACEDATA[0] J7 P0.12/TRACECLK J6 P0.13/QSPI[0] K10 P0.14/QSPI[1] K9 P0.15/QSPI[2] L9 P0.21 J4 P0.28/AIN7 E3 P0.30 C4 P0.31 C5 P0.29 E2 P0.10/TRACEDATA[1] J8 U1B nRF5340-CMAA P1.11 C6 P1.10 E4 P1.09 H2 P1.01 E10 P1.02/TWI J11 P1.03/TWI K12 P1.06 J3 P1.07 G3 P1.08 F3 P1.12 C7 P1.13 C8 P1.14 C9 P1.15 C10 P1.00 D10 P1.05 L3 P1.04 K3 U1C nRF5340-CMAA P1.10 P1.11 P1.12 P1.13 P1.14 P1.15 C13 100nF L2 2.2nH C19 N.C. C11 100nF L1 2.2nH ANT VSS C2 VSS B9 VSS K11 VSS K6 VSS E6 VSS D12 VSS B2 VSS A5 VSS E5 VSS E7 VSS E8 VSS F5 VSS F6 VSS F7 VSS F8 VSS G5 VSS G6 VSS G7 VSS G8 U1D nRF5340-CMAA SWDCLK SWDIO D_N D_P RESET Optional R1 2R2
Note: For PCB reference layouts, see the product page for the nRF5340 on www.nordicsemi.com.
Table 27. Bill of material for circuit configuration no. 4
Designator Value Description Footprint
C1 0.7 pF Capacitor, NP0, ±0.05 pF 0201
C2, C3, C5, C7, C10, C17 1.0 µF Capacitor, X7S, ±10% 0402
C4 2.2 nF Capacitor, X7R, ±10% 0201
C6, C8, C9, C11, C12, C13 100 nF Capacitor, X7S, ±10% 0201
C15 4.7 µF Capacitor, X7S, ±10% 0603
C16 4.7 µF Capacitor, X7R, ±10% 0603
C19 N.C. Not mounted 0201
L1, L2 2.2 nH High frequency chip inductor, ±5% 0201
R1 2.2 Ω Resistor, ±1%, 0.05 W 0201
U1 nRF5340-CMAA Multiprotocol Bluetooth Low Energy, IEEE 802.15.4, ANT, and 2.4GHz proprietary System on Chip WLCSP-95
X1 32 MHz Crystal SMD 2016, 32 MHz, Cl=8 pF, Total Tol: ±30 ppm. For frequency tolerance requirements, see 32 MHz crystal oscillator (HFXO). XTAL_2016
X2 32.768 kHz Crystal SMD 2012, 32.768 kHz, Cl=9 pF, Total Tol: ±50 ppm XTAL_2012

PCB layout example

The PCB layout in the following figure is a reference layout for Circuit configuration no. 1 for QKAA aQFN™94.

Note: Pay attention to how the capacitor C1 is grounded. It is not directly connected to the ground plane, but grounded via pin J31 and to the VSS die pad. This is done to create additional filtering of harmonic components.

For all available reference layouts, see the product page for nRF5340 on www.nordicsemi.com.

Figure 13. Top silk layer


Figure 14. Top layer


Figure 15. Mid layer 1


Figure 16. Mid layer 2


Figure 17. Bottom layer


PMIC support

The nRF53 Series is comprehensively supported by Nordic Semiconductor's own range of PMICs (Power Management Integrated Circuits). These PMICs are meticulously designed to enhance the performance and efficiency of the nRF53 Series devices. This integration ensures the longest battery life and the highest reliability for the end application. The synergy between the nRF53 Series and the Nordic PMICs highlights Nordic Semiconductor's commitment to providing a complete and cohesive solution for their customers' needs in wireless technology applications.