AHB multilayer enables parallel access paths between multiple masters and slaves in a system. Access is resolved using priorities.
Each bus master is connected to a slave device through one or more interconnection matrixes. The bus masters are assigned priorities that are used to resolve access when two (or more) bus masters request access to the same slave device. The following applies when assigning priorities:
- If two (or more) bus masters request access to the same slave device, the master with the highest priority is granted access first.
- If a higher priority bus master transaction is on-going, bus masters with lower priority are stalled. Either until the higher priority master has completed its transaction, or the higher priority master at any point pauses during its transaction. During this pause, the lower priority master in queue is temporarily granted access to the slave device until the higher priority master resumes its activity.
- If a lower priority bus master transaction is on-going, and a master with higher priority requests access to the same slave device, the lower priority bus master is stalled after the current word access has been completed. The slave transaction will continue following the rules above.
- Bus masters that have the same priority are mutually exclusive, and cannot be used concurrently.
Some peripherals, like I2S, do not have a safe stalling mechanism (not able to pause incoming data and no internal data buffering). Being a low priority bus master might cause loss of data for such peripherals upon bus contention. To avoid AHB bus contention when using multiple bus masters, apply one of the following guidelines:
- Avoid situations where more than one bus master is accessing the same slave.
- If more than one bus master is accessing the same slave, make sure that the bus bandwidth is not exhausted.
AHB multilayer priorities
Each master connected to the AHB multilayer is assigned a default natural priority.
| Bus master name | Natural relative priority | In/Out |
|---|---|---|
| CPU | Highest priority | I/O |
| Network core | I/O | |
| I2S | I/O | |
| PDM | I | |
| UARTE0, SPIM0, SPIS0, TWIM0, TWIS0 | I/O | |
| UARTE1, SPIM1, SPIS1, TWIM1, TWIS1 | I/O | |
| UARTE2, SPIM2, SPIS2, TWIM2, TWIS2 | I/O | |
| UARTE3, SPIM3, SPIS3, TWIM3, TWIS3 | I/O | |
| SAADC | I | |
| PWM0 | O | |
| PWM1 | O | |
| PWM2 | O | |
| PWM3 | O | |
| SPIM4 | I/O | |
| NFCT | I/O | |
| CC312 | I/O | |
| USBD | I/O | |
| QSPI | Lowest priority | I/O |