UICR — User information configuration registers

The user information configuration registers (UICRs) are non-volatile memory (NVM) registers for configuring user specific settings and storing secure cryptographic keys or OTP values.

The cryptographic key part of the UICR (addresses starting at 0x100 and higher) is handled by the Key Management Unit (KMU), see KMU — Key management unit for more information.

For information on writing registers, see NVMC — Non-volatile memory controller and Memory.

Any access, both read and write, to UICR must be a full 32-bit word aligned to a 32-bit address.

Note: UICR is not accessible from the network core.

Registers

Instances


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
UICR	APPLICATION	0x00FF8000	HF	S	NA	No	User information configuration registers

Register overview


Register	Offset	Description
APPROTECT	0x000	Access port protection
VREGHVOUT	0x010	Output voltage from the high voltage (VREGH) regulator stage. The maximum output voltage from this stage is given as VDDH - VREGHDROP.
HFXOCNT	0x014	HFXO startup counter
SECUREAPPROTECT	0x01C	Secure access port protection
ERASEPROTECT	0x020	Erase protection
TINSTANCE	0x024	SW-DP Target instance
NFCPINS	0x028	Setting of pins dedicated to NFC functionality: NFC antenna or GPIO
OTP[n]	0x100	One time programmable memory
KEYSLOT.CONFIG[n].DEST	0x400	Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3]) will be pushed by KMU. Note that this address must match that of a peripherals APB mapped write-only key registers, else the KMU can push this key value into an address range which the CPU can potentially read.
KEYSLOT.CONFIG[n].PERM	0x404	Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF.
KEYSLOT.KEY[n].VALUE[o]	0x800	Define bits [31+o32:0+o32] of value assigned to KMU key slot.

APPROTECT

Address offset: 0x000

Access port protection


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PALL										Blocks debugger read/write access to all CPU registers and memory mapped addresses. Using any value except Unprotected will lead to the protection being enabled. Bits with value '1' can be written to '0'. Bits with value '0' cannot be written to '1'.
			Unprotected	0x50FA50FA								Unprotected
			Protected	0x00000000								Protected

VREGHVOUT

Address offset: 0x010

Output voltage from the high voltage (VREGH) regulator stage. The maximum output voltage from this stage is given as VDDH - VREGHDROP.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	VREGHVOUT										VREGH regulator output voltage.
			1V8	0								1.8 V
			2V1	1								2.1 V
			2V4	2								2.4 V
			2V7	3								2.7 V
			3V0	4								3.0 V
			3V3	5								3.3 V
			DEFAULT	7								Default voltage: 1.8 V

HFXOCNT

Address offset: 0x014

HFXO startup counter

The CLKSTARTED events are generated after the HFXO power up time + the HFXOCNT-defined debounce time + PLL lock time has elapsed. If the HFXO has already been requested by another clock source and is already running, the CLKSTARTED event is generated as soon as the PLL has locked.

Note: When HFXOCNT field of this register is 0xFF, e.g. after UICR being erased, a debounce time of (4*64 us + 0.5 us) is used


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												A	A	A	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	HFXOCNT										HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us
			MinDebounceTime	0								Min debounce time = (0*64 us + 0.5 us)
			MaxDebounceTime	254								Max debounce time = (254*64 us + 0.5 us)
			DefaultDebounceTime	255								Default debounce time for erased UICR = 4*64 us + 0.5 us

SECUREAPPROTECT

Address offset: 0x01C

Secure access port protection


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PALL										Blocks debugger read/write access to all secure CPU registers and secure memory mapped addresses. Using any value except Unprotected will lead to the protection being enabled. Bits with value '1' can be written to '0'. Bits with value '0' cannot be written to '1'.
			Unprotected	0x50FA50FA								Unprotected
			Protected	0x00000000								Protected

ERASEPROTECT

Address offset: 0x020

Erase protection


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PALL										Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality. Using any value except Unprotected will lead to the protection being enabled.
			Unprotected	0xFFFFFFFF								Unprotected
			Protected	0x00000000								Protected

TINSTANCE

Address offset: 0x024

SW-DP Target instance


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	TINSTANCE										TINSTANCE bits are negated and used in the SW-DP DLPIDR.TINSTANCE field. E.g. 0xF in this field is translated to 0x0 in DLPIDR.TINSTANCE field.

NFCPINS

Address offset: 0x028

Setting of pins dedicated to NFC functionality: NFC antenna or GPIO

Note: When used as NFC antenna pin, the corresponding pin must be controlled by the application core, and the GPIO PIN_CNF register initialized to its reset value.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	PROTECT										Setting of pins dedicated to NFC functionality
			Disabled	0								Operation as GPIO pins. Same protection as normal GPIO pins
			NFC	1								Operation as NFC antenna pins. Configures the protection for NFC operation

OTP[n] (n=0..191)

Address offset: 0x100 + (n × 0x4)

One time programmable memory


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	B	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW1	LOWER										Lower half word Can only be written to a non 0xFFFF value once.
B	RW1	UPPER										Upper half word Can only be written to a non 0xFFFF value once.

KEYSLOT.CONFIG[n].DEST (n=0..127)

Address offset: 0x400 + (n × 0x8)

Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3]) will be pushed by KMU. Note that this address must match that of a peripherals APB mapped write-only key registers, else the KMU can push this key value into an address range which the CPU can potentially read.

Note: Writing/reading this register requires the KMU SELECTKEYSLOT register to be set to n+1.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	DEST										Secure APB destination address

KEYSLOT.CONFIG[n].PERM (n=0..127)

Address offset: 0x404 + (n × 0x8)

Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF.

Note: Writing/reading this register requires the KMU SELECTKEYSLOT register to be set to n+1.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																			D														C	B	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	WRITE										Write permission for key slot
			Disabled	0								Disable write to the key value registers
			Enabled	1								Enable write to the key value registers
B	RW	READ										Read permission for key slot
			Disabled	0								Disable read from key value registers
			Enabled	1								Enable read from key value registers
C	RW	PUSH										Push permission for key slot
			Disabled	0								Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled
			Enabled	1								Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address!
D	RW	STATE										Revocation state for the key slot Note that it is not possible to undo a key revocation by writing the value '1' to this field
			Revoked	0								Key value registers can no longer be read or pushed
			Active	1								Key value registers are readable (if enabled) and can be pushed (if enabled)

KEYSLOT.KEY[n].VALUE[o] (n=0..127) (o=0..3)

Address offset: 0x800 + (n × 0x10) + (o × 0x4)

Define bits [31+o*32:0+o*32] of value assigned to KMU key slot.

Note: Writing/reading this register requires the KMU SELECTKEYSLOT register to be set to n+1.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	VALUE										Define bits [31+o32:0+o32] of value assigned to KMU key slot