I2S — Inter-IC sound interface

The I²S (Inter-IC Sound) module, supports the original two-channel I²S format, and left- or right-aligned formats. It implements EasyDMA for sample transfer directly to and from RAM without CPU intervention.

The I²S peripheral has the following main features:

Master and Slave mode
Simultaneous bidirectional (TX and RX) audio streaming
Original I²S and left- or right-aligned format
32, 24, 16 and 8-bit sample widths
Separate sample and word widths
Low-jitter master clock generator
Various sample rates

I2S block diagram — Figure 1. I²S master

Mode

The I²S protocol specification defines two modes of operation, Master and Slave.

The I²S mode decides which of the two sides (master or slave) shall provide the clock signals LRCK and SCK, and these signals are always supplied by the master to the slave.

Transmitting and receiving

The I²S module supports both transmission (TX) and reception (RX) of serial data. In both cases the serial data is shifted synchronously to the clock signals SCK and LRCK.

TX data is written to the SDOUT pin on the falling edge of SCK, and RX data is read from the SDIN pin on the rising edge of SCK. The most significant bit (MSB) is always transmitted first.

Note: When starting a transmission in master mode, the first frame is filled with zeros.

TX and RX are available in both Master and Slave modes and can be enabled/disabled independently in the CONFIG.TXEN and CONFIG.RXEN.

Transmission and/or reception is started by triggering the START task. With transmission enabled in CONFIG.TXEN), the TXPTRUPD event will be generated for every number of transmitted data words given by RXTXD.MAXCNT. Each data word contains one or more samples. The TXPTRUPD event is generated just before MAXCNT number of data words have been transmitted. Similarly, with reception enabled in CONFIG.RXEN, the RXPTRUPD event will be generated for every received data word given by RXTXD.MAXCNT. The RXPTRUPD event is generated just after MAXCNT number of data words have been received.

The FRAMESTART event is generated synchronously to the active LRCK edge at the beginning of a frame after transmitting RXTXD.MAXCNT data words. The initial FRAMESTART event is generated at the first active edge of LRCK after the START task has been triggered. The FRAMESTART event is only defined for transmitting full left and right sample pairs. If MAXCNT is configured so that the frame ends between the left and right sample pairs, the FRAMESTART event is not generated. This occurs for the following combinations of SWIDTH and MAXCNT:

Table 1. Restrictions on combinations of SWIDTH and MAXCNT for correct FRAMESTART
SWIDTH	MAXCNT restriction
24Bit	Only even numbers (2,4,6, etc)
32	Only even numbers (2, 4, 6, etc)
24BitIn32	Only even numbers (2, 4, 6, etc)

Transmitting and receiving. CONFIG.FORMAT = Aligned, CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Stereo, RXTXD.MAXCNT = 1. — Figure 2. Transmitting and receiving. CONFIG.FORMAT = Aligned, CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Stereo, RXTXD.MAXCNT = 1

Left right clock (LRCK)

The left right clock (LRCK), often referred to as word clock, sample clock, or word select in I²S context, is the clock defining the frames in serial bitstreams sent and received on SDOUT and SDIN, respectively.

In I2S format, each frame contains one left and/or right sample pair. The left sample is transferred during the low half period of LRCK, followed by the right sample being transferred during the high half period of LRCK.

In Aligned format, each frame contains one left and/or right sample pair. The left sample is transferred during the high half period of LRCK, followed by the right sample being transferred during the low half period of LRCK.

For mono, the frame will contain only zeros for the unused half period of LRCK.

Consequently, the LRCK frequency is equivalent to the audio sample rate.

When operating in Master mode, the LRCK is generated from the MCK, and the frequency of LRCK is then given as:

LRCK = MCK / CONFIG.RATIO

LRCK always toggles around the falling edge of the serial clock SCK.

Serial clock (SCK)

The serial clock (SCK), often referred to as the serial bit clock, pulses once for each data bit being transferred on the serial data lines SDIN and SDOUT.

When operating in Master mode, the SCK is generated from the MCK, and the frequency of SCK is then given as:

SCK = 2 * LRCK * CONFIG.SWIDTH

The falling edge of the SCK falls on the toggling edge of LRCK.

When operating in Slave mode, SCK is provided by the external I²S master.

Master clock (MCK)

The master clock (MCK) is the clock from which LRCK and SCK are derived when operating in Master mode.

The master clock generator always needs to be enabled when in Master mode, but the generator can also be enabled when in Slave mode. Enabling the generator when in Slave mode can be useful in the case where the external master is not able to generate its own master clock.

MCK is generated from the clock source selected in the CONFIG.CLKCONFIG and CONFIG.MCKFREQ registers.

The following equation can be used to calculate the value of CONFIG.MCKFREQ for given MCK and clock source frequency:

The parameter f_MCK is the requested MCK clock frequency in Hz, and f_source is the frequency of the selected clock source in Hz. Because of rounding errors, an accurate MCK clock may not be achievable. The equation does not take into account the maximum register value of CONFIG.MCKFREQ.

The actual MCK frequency can be calculated using the equation below.

The clock error can be calculated using the equation below. The error e is the percentage difference from the requested f_MCK frequency.

The master clock generator does not add any jitter to the clock source chosen.

The master clock generator is enabled/disabled using CONFIG.MCKEN, and the generator is started or stopped by the START or STOP tasks respectively.

The MCK frequency can be adjusted on-the-fly:

For PCLK32M, by using MCKFREQ
For ACLK, by adjusting the audio clock source, see CLOCK — Clock control.

In Master mode, the LRCK and the SCK frequencies are closely related as both are derived from MCK and set indirectly through CONFIG.RATIO and CONFIG.SWIDTH.

When configuring these registers, the user is responsible for fulfilling the following requirements:

The SCK frequency can never exceed the MCK frequency.
The MCK/LRCK ratio shall be a multiple of 2 * CONFIG.SWIDTH.

The MCK signal can be routed to an output pin (specified in PSEL.MCK) to supply external I²S devices that require the MCK to be supplied from the outside.

When operating in Slave mode, the I²S module does not use the MCK and the MCK generator does not need to be enabled.

Relation between RATIO, MCK and LRCK. — Figure 6. Relation between RATIO, MCK and LRCK

Clock source selection

The clock source for the master clock generator can be selected in the register CONFIG.CLKCONFIG. Choose one of the following clocks as the clock source:

32 MHz peripheral clock (PCLK32M), synchronous to HFCLK.
Audio PLL clock (ACLK) with configurable frequency.

To improve the master clock accuracy and jitter performance, it is recommended (but not mandatory) that the PCLK32M source is running off the HFXO instead of the HFINT oscillator. The ACLK source requires the use of HFXO. See CLOCK — Clock control for more information about starting HFXO for the relevant clock source.

The master clock generator can be bypassed so the MCK clock is derived directly from the input source. This can be configured in the BYPASS field of register CONFIG.CLKCONFIG.

Configuration examples

Configuration examples for CLKCONFIG = PCLK32M and Configuration examples for CLKCONFIG = ACLK show some configuration examples for popular sample rates, using both the 32 MHz master clock and the Audio PLL clock source.

Table 2. Configuration examples for CLKCONFIG = PCLK32M
Source frequency [Hz]	Requested LRCK [Hz]	RATIO	Requested MCK [Hz]	MCKFREQ	MCK [Hz]	LRCK [Hz]	LRCK error [%]
32000000	16000	32	512000	68173824	507936	15873	-0.8
32000000	16000	64	1024000	135274496	1032258	16129	0.8
32000000	16000	256	4096000	516685824	4000000	15625	-2.3
32000000	32000	32	1024000	135274496	1032258	32258	0.8
32000000	32000	64	2048000	266350592	2000000	31250	-2.3
32000000	32000	256	8192000	974741504	8000000	31250	-2.3
32000000	44100	32	1411200	185319424	1391304	43478	-1.4
32000000	44100	64	2822400	362815488	2909090	45455	3.1
32000000	48000	32	1536000	201326592	1523809	47619	-0.8
32000000	48000	64	3072000	393428992	3200000	50000	4.2
32000000	96000	32	3072000	393428992	3200000	100000	4.2
32000000	96000	64	6144000	752402432	6400000	100000	4.2

Table 3. Configuration examples for CLKCONFIG = ACLK
Source frequency [Hz]	Requested LRCK [Hz]	RATIO	Requested MCK [Hz]	MCKFREQ	MCK [Hz]	LRCK [Hz]
11289600	44100	32	1411200	505286656	1411200	44100
11289600	44100	64	2822400	954433536	2822400	44100
12288000	16000	32	510000	175304704	512000	16000
12288000	16000	64	1024000	343597056	1024000	16000
12288000	32000	32	1024000	343597056	1024000	32000
12288000	32000	64	2048000	660762624	2048000	32000
12288000	48000	32	1536000	505286656	1536000	48000
12288000	48000	64	3072000	954433536	3072000	48000
12288000	96000	32	3072000	954433536	3072000	96000

Width, alignment and format

The register CONFIG.SWIDTH defines the sample width of the data read and written to memory, as well as the number of SCK clock cycles per half-frame. Figure Aligned format, with CONFIG.SWIDTH configured to 16 bit samples in a 16 bit half-frame illustrates a configuration with identical sample and half-frame widths. The number of SCK pulses matches the number of sample bits. Aligned format, with CONFIG.SWIDTH configured to 16-bit samples in a 24-bit half-frame illustrates a configuration with greater half-frame width than sample width. The number of SCK pulses are greater than the number of sample bits, with the sample being left-aligned in the half-frame.

Aligned format, with CONFIG.SWIDTH configured to 16-bit samples in a 16-bit half-frame. — Figure 7. Aligned format, with CONFIG.SWIDTH configured to 16 bit samples in a 16 bit half-frame

Aligned format, with CONFIG.SWIDTH configured to 16-bit samples in a 24-bit half-frame. — Figure 8. Aligned format, with CONFIG.SWIDTH configured to 16-bit samples in a 24-bit half-frame

The register CONFIG.FORMAT is used to choose whether a word shall be aligned on the LRCK edge, or be delayed one bit period after this edge:

When using Aligned format, the first bit in a half-frame gets sampled on the first rising edge of SCK following a LRCK edge, as illustrated in Aligned format. Identical sample width and half-frame width. Left sample on high level of LRCK . The left sample is transferred during the high half period of LRCK.
When using I²S format, the first bit in a half-frame (containing one left or right sample) gets sampled on the second rising edge of the SCK after a LRCK edge, as illustrated in I2S format. Identical sample width and half-frame width. Left sample on low level of LRCK . The left sample is transferred during the low half period of LRCK.

Figure 9. Aligned format. Identical sample width and half-frame width. Left sample on high level of LRCK

I2S format. Identical sample width and half-frame width. — Figure 10. I²S format. Identical sample width and half-frame width. Left sample on low level of LRCK

If the half-frame width differs from the sample width, the sample value can be either right or left-aligned inside a half-frame, as specified in CONFIG.ALIGN

When using left-alignment, each half-frame starts with the MSB of the sample value, as illustrated by CONFIG.ALIGN set to left justified .
When using right-alignment, each half-frame ends with the LSB of the sample value. This is illustrated in CONFIG.ALIGN set to right justified .

CONFIG.ALIGN equalling left justified. — Figure 11. CONFIG.ALIGN set to left justified

CONFIG.ALIGN equalling right justified. — Figure 12. CONFIG.ALIGN set to right justified

Slave mode considerations

In Slave mode, the sample width does not need to equal the half-frame width, or even frame size. This means that there can be extra or fewer SCK pulses per half-frame than what the sample and half-frame widths specified in CONFIG.SWIDTH require.

In cases where left-alignment is used, and the number of SCK pulses per half-frame is higher than the configured width, the following will apply:

For data received on SDIN, all bits after the least significant bit (LSB) of the word value will be discarded.
For data sent on SDOUT, all bits after the LSB of the word value will be 0.

In cases where left-alignment is used, and the number of SCK pulses per frame is lower than the word width, the following will apply:

Data sent and received on SDOUT and SDIN will be truncated with the LSBs being removed first.

In cases where right-alignment is used, and the number of SCK pulses per frame is higher than the configured width, the following will apply:

For data received on SDIN, all bits before the MSB of the word value will be discarded.
For data sent on SDOUT, all bits after the LSB of the word value will be 0 (same behavior as for left-alignment).

In cases where right-alignment is used, and the number of SCK pulses per frame is lower than the configured width, the following will apply:

Data received on SDIN will be sign-extended to the same number of bits as the sample width before being written to memory.
Data sent on SDOUT will be truncated with the LSBs being removed first (same behavior as for left-alignment).

EasyDMA

The I²S module implements EasyDMA for accessing internal Data RAM without CPU intervention.

The source and destination pointers for the TX and RX data are configured in TXD.PTR and RXD.PTR. The memory pointed to by these pointers will only be read or written when TX or RX are enabled in CONFIG.TXEN, and CONFIG.RXEN.

The addresses written to the pointer registers TXD.PTR and RXD.PTR are double-buffered in hardware. These double buffers are updated for every number of transmitted data words given by RXTXD.MAXCNT read from/written to memory. The events TXPTRUPD and RXPTRUPD are generated whenever the TXD.PTR and RXD.PTR are transferred to these double buffers.

If TXD.PTR is not pointing to the Data RAM region when transmission is enabled, or RXD.PTR is not pointing to the Data RAM region when reception is enabled, an EasyDMA transfer may result in a HardFault and/or memory corruption. See Memory for more information about the different memory regions.

Due to the nature of I²S, where the number of transmitted samples always equals the number of received samples (at least when both TX and RX are enabled), one common register RXTXD.MAXCNT is used for specifying the sizes of these two memory buffers. The size of the buffers is specified in a number of 32-bit words. Such a 32-bit memory word can either contain one 32-bit sample, one right-aligned 24-bit sample sign extended to 32-bit, two 16-bit samples or four 8-bit samples.

In Stereo mode (CONFIG.CHANNELS=Stereo), the samples are stored as left and right sample pairs in memory. Memory mapping for 8-bit stereo. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Stereo., Memory mapping for 16-bit stereo. CONFIG.SWIDTH = 16Bit, CONFIG.CHANNELS = Stereo. and Memory mapping for 24-bit stereo. CONFIG.SWIDTH = 24Bit, CONFIG.CHANNELS = Stereo. show how the samples are mapped to memory in this mode. The mapping is valid for both RX and TX.

In Mono mode (CONFIG.CHANNELS=Left or Right), RX sample from only one channel in the frame is stored in memory, the other channel sample is ignored. Memory mapping for 8-bit mono. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Left., Memory mapping for 16-bit mono, left channel only. CONFIG.SWIDTH = 16Bit, CONFIG.CHANNELS = Left. and Memory mapping for 24-bit mono, left channel only. CONFIG.SWIDTH = 24Bit, CONFIG.CHANNELS = Left. show how RX samples are mapped to memory in this mode. For TX, the same outgoing sample read from memory is transmitted on both left and right in a frame, resulting in a mono output stream.

Figure 13. Memory mapping for 8-bit stereo. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Stereo.

Figure 14. Memory mapping for 8-bit mono. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Left.

Figure 15. Memory mapping for 16-bit stereo. CONFIG.SWIDTH = 16Bit, CONFIG.CHANNELS = Stereo.

Figure 16. Memory mapping for 16-bit mono, left channel only. CONFIG.SWIDTH = 16Bit, CONFIG.CHANNELS = Left.

Figure 17. Memory mapping for 24-bit stereo. CONFIG.SWIDTH = 24Bit, CONFIG.CHANNELS = Stereo.

Figure 18. Memory mapping for 24-bit mono, left channel only. CONFIG.SWIDTH = 24Bit, CONFIG.CHANNELS = Left.

Figure 19. Memory mapping for 32-bit stereo. CONFIG.SWIDTH = 32Bit, CONFIG.CHANNELS = Stereo.

Figure 20. Memory mapping for 32-bit mono, left channel only. CONFIG.SWIDTH = 32Bit, CONFIG.CHANNELS = Left.

Module operation

Described here is a typical operating procedure for the I²S module.

Configure the I²S module using the CONFIG registers

// Enable reception
NRF_I2S->CONFIG.RXEN = (I2S_CONFIG_RXEN_RXEN_Enabled <<
                                       I2S_CONFIG_RXEN_RXEN_Pos);
// Enable transmission
NRF_I2S->CONFIG.TXEN = (I2S_CONFIG_TXEN_TXEN_Enabled <<
                                       I2S_CONFIG_TXEN_TXEN_Pos);
// Enable MCK generator
NRF_I2S->CONFIG.MCKEN = (I2S_CONFIG_MCKEN_MCKEN_Enabled <<
                                       I2S_CONFIG_MCKEN_MCKEN_Pos);
// MCKFREQ = 4 MHz
NRF_I2S->CONFIG.MCKFREQ = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 <<
                                       I2S_CONFIG_MCKFREQ_MCKFREQ_Pos;
// Ratio = 256 
NRF_I2S->CONFIG.RATIO = I2S_CONFIG_RATIO_RATIO_256X <<
                                       I2S_CONFIG_RATIO_RATIO_Pos;
// MCKFREQ = 4 MHz and Ratio = 256 gives sample rate = 15.625 ks/s
// Sample width = 16 bit
NRF_I2S->CONFIG.SWIDTH = I2S_CONFIG_SWIDTH_SWIDTH_16Bit <<
                                       I2S_CONFIG_SWIDTH_SWIDTH_Pos;
// Alignment = Left
NRF_I2S->CONFIG.ALIGN = I2S_CONFIG_ALIGN_ALIGN_Left <<
                                       I2S_CONFIG_ALIGN_ALIGN_Pos;
// Format = I2S
NRF_I2S->CONFIG.FORMAT = I2S_CONFIG_FORMAT_FORMAT_I2S <<
                                       I2S_CONFIG_FORMAT_FORMAT_Pos;
// Use stereo 
NRF_I2S->CONFIG.CHANNELS = I2S_CONFIG_CHANNELS_CHANNELS_Stereo <<
                                       I2S_CONFIG_CHANNELS_CHANNELS_Pos;

Map IO pins using the PINSEL registers

// MCK routed to pin 0
NRF_I2S->PSEL.MCK = (0 << I2S_PSEL_MCK_PIN_Pos) | 
                    (I2S_PSEL_MCK_CONNECT_Connected <<
                                                 I2S_PSEL_MCK_CONNECT_Pos);
// SCK routed to pin 1
NRF_I2S->PSEL.SCK = (1 << I2S_PSEL_SCK_PIN_Pos) | 
                    (I2S_PSEL_SCK_CONNECT_Connected <<
                                                 I2S_PSEL_SCK_CONNECT_Pos); 
// LRCK routed to pin 2
NRF_I2S->PSEL.LRCK = (2 << I2S_PSEL_LRCK_PIN_Pos) | 
                     (I2S_PSEL_LRCK_CONNECT_Connected <<
                                                 I2S_PSEL_LRCK_CONNECT_Pos); 
// SDOUT routed to pin 3
NRF_I2S->PSEL.SDOUT = (3 << I2S_PSEL_SDOUT_PIN_Pos) | 
                      (I2S_PSEL_SDOUT_CONNECT_Connected <<
                                                 I2S_PSEL_SDOUT_CONNECT_Pos);
// SDIN routed on pin 4
NRF_I2S->PSEL.SDIN = (4 << I2S_PSEL_SDIN_PIN_Pos) | 
                     (I2S_PSEL_SDIN_CONNECT_Connected <<
                                                 I2S_PSEL_SDIN_CONNECT_Pos);

Configure TX and RX data pointers using the TXD, RXD and RXTXD registers

NRF_I2S->TXD.PTR = my_tx_buf;
NRF_I2S->RXD.PTR = my_rx_buf;
NRF_I2S->TXD.MAXCNT = MY_BUF_SIZE;

Enable the I²S module using the ENABLE register
```
NRF_I2S->ENABLE = 1;
```
Start audio streaming using the START task
```
NRF_I2S->TASKS_START = 1;
```

Handle received and transmitted data when receiving the TXPTRUPD and RXPTRUPD events

if(NRF_I2S->EVENTS_TXPTRUPD  != 0)
{
    NRF_I2S->TXD.PTR = my_next_tx_buf;
    NRF_I2S->EVENTS_TXPTRUPD = 0;
}

if(NRF_I2S->EVENTS_RXPTRUPD != 0)
{
    NRF_I2S->RXD.PTR = my_next_rx_buf;
    NRF_I2S->EVENTS_RXPTRUPD = 0;
}

Pin configuration

The MCK, SCK, LRCK, SDIN and SDOUT signals associated with the I²S module are mapped to physical pins according to the pin numbers specified in the PSEL.x registers.

These pins are acquired whenever the I²S module is enabled through the register ENABLE.

When a pin is acquired by the I²S module, the direction of the pin (input or output) will be configured automatically, and any pin direction setting done in the GPIO module will be overridden. The directions for the various I²S pins are shown below in GPIO configuration before enabling peripheral (Master mode) and GPIO configuration before enabling peripheral (Slave mode).

To secure correct signal levels on the pins in System OFF mode, and when the I²S module is disabled, these pins must be configured in the GPIO peripheral directly.

Table 4. GPIO configuration before enabling peripheral (Master mode)
I²S signal	I²S pin	Direction	Output value
MCK	As specified in PSEL.MCK	Output	0
LRCK	As specified in PSEL.LRCK	Output	0
SCK	As specified in PSEL.SCK	Output	0
SDIN	As specified in PSEL.SDIN	Input	Not applicable
SDOUT	As specified in PSEL.SDOUT	Output	0

Table 5. GPIO configuration before enabling peripheral (Slave mode)
I²S signal	I²S pin	Direction	Output value
MCK	As specified in PSEL.MCK	Output	0
LRCK	As specified in PSEL.LRCK	Input	Not applicable
SCK	As specified in PSEL.SCK	Input	Not applicable
SDIN	As specified in PSEL.SDIN	Input	Not applicable
SDOUT	As specified in PSEL.SDOUT	Output	0

Registers

Instances


Instance	Domain	Base address	TrustZone			Split access	Description
Instance	Domain	Base address	Map	Att	DMA	Split access	Description
I2S0 : S I2S0 : NS	APPLICATION	0x50028000 0x40028000	US	S	SA	No	Inter-IC sound interface

Configuration


Instance	Domain	Configuration
I2S0 : S I2S0 : NS	APPLICATION

Register overview


Register	Offset	Description
TASKS_START	0x000	Starts continuous I2S transfer. Also starts MCK generator when this is enabled
TASKS_STOP	0x004	Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated.
SUBSCRIBE_START	0x080	Subscribe configuration for task START
SUBSCRIBE_STOP	0x084	Subscribe configuration for task STOP
EVENTS_RXPTRUPD	0x104	The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin.
EVENTS_STOPPED	0x108	I2S transfer stopped.
EVENTS_TXPTRUPD	0x114	The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.
EVENTS_FRAMESTART	0x11C	Frame start event, generated on the active edge of LRCK
PUBLISH_RXPTRUPD	0x184	Publish configuration for event RXPTRUPD
PUBLISH_STOPPED	0x188	Publish configuration for event STOPPED
PUBLISH_TXPTRUPD	0x194	Publish configuration for event TXPTRUPD
PUBLISH_FRAMESTART	0x19C	Publish configuration for event FRAMESTART
INTEN	0x300	Enable or disable interrupt
INTENSET	0x304	Enable interrupt
INTENCLR	0x308	Disable interrupt
ENABLE	0x500	Enable I2S module
CONFIG.MODE	0x504	I2S mode
CONFIG.RXEN	0x508	Reception (RX) enable
CONFIG.TXEN	0x50C	Transmission (TX) enable
CONFIG.MCKEN	0x510	Master clock generator enable
CONFIG.MCKFREQ	0x514	I2S clock generator control
CONFIG.RATIO	0x518	MCK / LRCK ratio
CONFIG.SWIDTH	0x51C	Sample width
CONFIG.ALIGN	0x520	Alignment of sample within a frame
CONFIG.FORMAT	0x524	Frame format
CONFIG.CHANNELS	0x528	Enable channels
CONFIG.CLKCONFIG	0x52C	Clock source selection for the I2S module
RXD.PTR	0x538	Receive buffer RAM start address.
TXD.PTR	0x540	Transmit buffer RAM start address
RXTXD.MAXCNT	0x550	Size of RXD and TXD buffers
PSEL.MCK	0x560	Pin select for MCK signal
PSEL.SCK	0x564	Pin select for SCK signal
PSEL.LRCK	0x568	Pin select for LRCK signal
PSEL.SDIN	0x56C	Pin select for SDIN signal
PSEL.SDOUT	0x570	Pin select for SDOUT signal

TASKS_START

Address offset: 0x000

Starts continuous I2S transfer. Also starts MCK generator when this is enabled


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_START										Starts continuous I2S transfer. Also starts MCK generator when this is enabled
			Trigger	1								Trigger task

TASKS_STOP

Address offset: 0x004

Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_STOP										Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated.
			Trigger	1								Trigger task

SUBSCRIBE_START

Address offset: 0x080

Subscribe configuration for task START


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[0..255]								DPPI channel that task START will subscribe to
B	RW	EN
			Disabled	0								Disable subscription
			Enabled	1								Enable subscription

SUBSCRIBE_STOP

Address offset: 0x084

Subscribe configuration for task STOP


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[0..255]								DPPI channel that task STOP will subscribe to
B	RW	EN
			Disabled	0								Disable subscription
			Enabled	1								Enable subscription

EVENTS_RXPTRUPD

Address offset: 0x104

The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_RXPTRUPD										The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin.
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_STOPPED

Address offset: 0x108

I2S transfer stopped.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_STOPPED										I2S transfer stopped.
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_TXPTRUPD

Address offset: 0x114

The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_TXPTRUPD										The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_FRAMESTART

Address offset: 0x11C

Frame start event, generated on the active edge of LRCK


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_FRAMESTART										Frame start event, generated on the active edge of LRCK
			NotGenerated	0								Event not generated
			Generated	1								Event generated

PUBLISH_RXPTRUPD

Address offset: 0x184

Publish configuration for event RXPTRUPD


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[0..255]								DPPI channel that event RXPTRUPD will publish to
B	RW	EN
			Disabled	0								Disable publishing
			Enabled	1								Enable publishing

PUBLISH_STOPPED

Address offset: 0x188

Publish configuration for event STOPPED


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[0..255]								DPPI channel that event STOPPED will publish to
B	RW	EN
			Disabled	0								Disable publishing
			Enabled	1								Enable publishing

PUBLISH_TXPTRUPD

Address offset: 0x194

Publish configuration for event TXPTRUPD


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[0..255]								DPPI channel that event TXPTRUPD will publish to
B	RW	EN
			Disabled	0								Disable publishing
			Enabled	1								Enable publishing

PUBLISH_FRAMESTART

Address offset: 0x19C

Publish configuration for event FRAMESTART


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[0..255]								DPPI channel that event FRAMESTART will publish to
B	RW	EN
			Disabled	0								Disable publishing
			Enabled	1								Enable publishing

INTEN

Address offset: 0x300

Enable or disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												H		F			C	B
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
B	RW	RXPTRUPD										Enable or disable interrupt for event RXPTRUPD
			Disabled	0								Disable
			Enabled	1								Enable
C	RW	STOPPED										Enable or disable interrupt for event STOPPED
			Disabled	0								Disable
			Enabled	1								Enable
F	RW	TXPTRUPD										Enable or disable interrupt for event TXPTRUPD
			Disabled	0								Disable
			Enabled	1								Enable
H	RW	FRAMESTART										Enable or disable interrupt for event FRAMESTART
			Disabled	0								Disable
			Enabled	1								Enable

INTENSET

Address offset: 0x304

Enable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												H		F			C	B
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
B	RW	RXPTRUPD										Write '1' to enable interrupt for event RXPTRUPD
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
C	RW	STOPPED										Write '1' to enable interrupt for event STOPPED
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
F	RW	TXPTRUPD										Write '1' to enable interrupt for event TXPTRUPD
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
H	RW	FRAMESTART										Write '1' to enable interrupt for event FRAMESTART
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												H		F			C	B
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
B	RW	RXPTRUPD										Write '1' to disable interrupt for event RXPTRUPD
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
C	RW	STOPPED										Write '1' to disable interrupt for event STOPPED
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
F	RW	TXPTRUPD										Write '1' to disable interrupt for event TXPTRUPD
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
H	RW	FRAMESTART										Write '1' to disable interrupt for event FRAMESTART
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

ENABLE

Address offset: 0x500

Enable I2S module


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ENABLE										Enable I2S module
			Disabled	0								Disable
			Enabled	1								Enable

CONFIG.MODE

Address offset: 0x504

I2S mode


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	MODE										I2S mode
			Master	0								Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx.
			Slave	1								Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx

CONFIG.RXEN

Address offset: 0x508

Reception (RX) enable


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	RXEN										Reception (RX) enable
			Disabled	0								Reception disabled and now data will be written to the RXD.PTR address.
			Enabled	1								Reception enabled.

CONFIG.TXEN

Address offset: 0x50C

Transmission (TX) enable


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000001				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
ID	R/W	Field	Value ID	Value								Description
A	RW	TXEN										Transmission (TX) enable
			Disabled	0								Transmission disabled and now data will be read from the RXD.TXD address.
			Enabled	1								Transmission enabled.

CONFIG.MCKEN

Address offset: 0x510

Master clock generator enable


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000001				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
ID	R/W	Field	Value ID	Value								Description
A	RW	MCKEN										Master clock generator enable
			Disabled	0								Master clock generator disabled and PSEL.MCK not connected(available as GPIO).
			Enabled	1								Master clock generator running and MCK output on PSEL.MCK.

CONFIG.MCKFREQ

Address offset: 0x514

I2S clock generator control


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x20000000				0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	MCKFREQ										I2S MCK frequency configuration NOTE: Enumerations are deprecated, use MCKFREQ equation. NOTE: The 12 least significant bits of the register are ignored and shall be set to zero.
			32MDIV2	0x80000000								32 MHz / 2 = 16.0 MHz Deprecated, use MCKFREQ equation.
			32MDIV3	0x50000000								32 MHz / 3 = 10.6666667 MHz Deprecated, use MCKFREQ equation.
			32MDIV4	0x40000000								32 MHz / 4 = 8.0 MHz Deprecated, use MCKFREQ equation.
			32MDIV5	0x30000000								32 MHz / 5 = 6.4 MHz Deprecated, use MCKFREQ equation.
			32MDIV6	0x28000000								32 MHz / 6 = 5.3333333 MHz Deprecated, use MCKFREQ equation.
			32MDIV8	0x20000000								32 MHz / 8 = 4.0 MHz Deprecated, use MCKFREQ equation.
			32MDIV10	0x18000000								32 MHz / 10 = 3.2 MHz Deprecated, use MCKFREQ equation.
			32MDIV11	0x16000000								32 MHz / 11 = 2.9090909 MHz Deprecated, use MCKFREQ equation.
			32MDIV15	0x11000000								32 MHz / 15 = 2.1333333 MHz Deprecated, use MCKFREQ equation.
			32MDIV16	0x10000000								32 MHz / 16 = 2.0 MHz Deprecated, use MCKFREQ equation.
			32MDIV21	0x0C000000								32 MHz / 21 = 1.5238095 MHz Deprecated, use MCKFREQ equation.
			32MDIV23	0x0B000000								32 MHz / 23 = 1.3913043 MHz Deprecated, use MCKFREQ equation.
			32MDIV30	0x08800000								32 MHz / 30 = 1.0666667 MHz Deprecated, use MCKFREQ equation.
			32MDIV31	0x08400000								32 MHz / 31 = 1.0322581 MHz Deprecated, use MCKFREQ equation.
			32MDIV32	0x08000000								32 MHz / 32 = 1.0 MHz Deprecated, use MCKFREQ equation.
			32MDIV42	0x06000000								32 MHz / 42 = 0.7619048 MHz Deprecated, use MCKFREQ equation.
			32MDIV63	0x04100000								32 MHz / 63 = 0.5079365 MHz Deprecated, use MCKFREQ equation.
			32MDIV125	0x020C0000								32 MHz / 125 = 0.256 MHz Deprecated, use MCKFREQ equation.

CONFIG.RATIO

Address offset: 0x518

MCK / LRCK ratio


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																A	A	A	A
Reset 0x00000006				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	0
ID	R/W	Field	Value ID	Value								Description
A	RW	RATIO										MCK / LRCK ratio
			32X	0								LRCK = MCK / 32
			48X	1								LRCK = MCK / 48
			64X	2								LRCK = MCK / 64
			96X	3								LRCK = MCK / 96
			128X	4								LRCK = MCK / 128
			192X	5								LRCK = MCK / 192
			256X	6								LRCK = MCK / 256
			384X	7								LRCK = MCK / 384
			512X	8								LRCK = MCK / 512

CONFIG.SWIDTH

Address offset: 0x51C

Sample width


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																	A	A	A
Reset 0x00000001				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
ID	R/W	Field	Value ID	Value								Description
A	RW	SWIDTH										Sample and half-frame width
			8Bit	0								8 bit sample.
			16Bit	1								16 bit sample.
			24Bit	2								24 bit sample.
			32Bit	3								32 bit sample.
			8BitIn16	4								8 bit sample in a 16-bit half-frame.
			8BitIn32	5								8 bit sample in a 32-bit half-frame.
			16BitIn32	6								16 bit sample in a 32-bit half-frame.
			24BitIn32	7								24 bit sample in a 32-bit half-frame.

CONFIG.ALIGN

Address offset: 0x520

Alignment of sample within a frame


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ALIGN										Alignment of sample within a frame
			Left	0								Left-aligned.
			Right	1								Right-aligned.

CONFIG.FORMAT

Address offset: 0x524

Frame format


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	FORMAT										Frame format
			I2S	0								Original I2S format.
			Aligned	1								Alternate (left- or right-aligned) format.

CONFIG.CHANNELS

Address offset: 0x528

Enable channels


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																		A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHANNELS										Enable channels
			Stereo	0								Stereo.
			Left	1								Left only.
			Right	2								Right only.

CONFIG.CLKCONFIG

Address offset: 0x52C

Clock source selection for the I2S module


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																											B								A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CLKSRC										Clock source selection
			PCLK32M	0								32MHz peripheral clock
			ACLK	1								Audio PLL clock
B	RW	BYPASS										Bypass clock generator. MCK will be equal to source input. If bypass is enabled the MCKFREQ setting has no effect.
			Disable	0								Disable bypass
			Enable	1								Enable bypass

RXD.PTR

Address offset: 0x538

Receive buffer RAM start address.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PTR										Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. Note: See the memory chapter for details about which memories are available for EasyDMA.

TXD.PTR

Address offset: 0x540

Transmit buffer RAM start address


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PTR										Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. Note: See the memory chapter for details about which memories are available for EasyDMA.

RXTXD.MAXCNT

Address offset: 0x550

Size of RXD and TXD buffers


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																						A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	MAXCNT										Size of RXD and TXD buffers in number of 32 bit words

PSEL.MCK

Address offset: 0x560

Pin select for MCK signal


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				C																										B	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	PIN		[0..31]								Pin number
B	RW	PORT		[0..1]								Port number
C	RW	CONNECT										Connection
			Disconnected	1								Disconnect
			Connected	0								Connect

PSEL.SCK

Address offset: 0x564

Pin select for SCK signal


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				C																										B	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	PIN		[0..31]								Pin number
B	RW	PORT		[0..1]								Port number
C	RW	CONNECT										Connection
			Disconnected	1								Disconnect
			Connected	0								Connect

PSEL.LRCK

Address offset: 0x568

Pin select for LRCK signal


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				C																										B	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	PIN		[0..31]								Pin number
B	RW	PORT		[0..1]								Port number
C	RW	CONNECT										Connection
			Disconnected	1								Disconnect
			Connected	0								Connect

PSEL.SDIN

Address offset: 0x56C

Pin select for SDIN signal


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				C																										B	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	PIN		[0..31]								Pin number
B	RW	PORT		[0..1]								Port number
C	RW	CONNECT										Connection
			Disconnected	1								Disconnect
			Connected	0								Connect

PSEL.SDOUT

Address offset: 0x570

Pin select for SDOUT signal


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				C																										B	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	RW	PIN		[0..31]								Pin number
B	RW	PORT		[0..1]								Port number
C	RW	CONNECT										Connection
			Disconnected	1								Disconnect
			Connected	0								Connect

Electrical specification

I2S timing specification


Symbol	Description	Min.	Typ.	Max.	Units
t_{S_SDIN}	SDIN setup time before SCK rising	20			ns
t_{H_SDIN}	SDIN hold time after SCK rising	15			ns
t_{S_SDOUT}	SDOUT setup time after SCK falling			50	ns
t_{H_SDOUT}	SDOUT hold time after SCK falling	13			ns
t_{SCK_LRCK}	SCLK falling to LRCK edge	-5	0	5	ns
f_MCK	MCK frequency			12288	kHz
f_LRCK	LRCK frequency			96	kHz
f_SCK	SCK frequency			8000	kHz
DC_CK	Clock duty cycle (MCK, LRCK, SCK)	45		55	%