Block diagram

nRF5340 Product Specification

nRF5340 Product Specification
Revision history
About this document
Product overview
Power and clock management
Current consumption
Power supply modes and regulators
POWER — Power control
REGULATORS — Regulator control
USBREG — USB regulator control
VREQCTRL — Voltage request control
RESET — Reset control
CLOCK — Clock control
OSCILLATORS — Oscillator control
Application core
Block diagram
CPU
Memory
Core components
CACHE — Instruction/data cache
FICR — Factory information configuration registers
UICR — User information configuration registers
AHB multilayer
Network core
Block diagram
CPU
Memory
Core components
FICR — Factory information configuration registers
UICR — User information configuration registers
AHB multilayer
Peripherals
Peripheral interface
EasyDMA
ACL — Access control lists
AAR — Accelerated address resolver
CCM — AES CCM mode encryption
COMP — Comparator
CRYPTOCELL — Arm TrustZone CryptoCell 312
DCNF — Domain configuration
DPPI — Distributed programmable peripheral interconnect
ECB — AES electronic codebook mode encryption
EGU — Event generator unit
FPU — Floating point unit (FPU) exceptions
GPIO — General purpose input/output
GPIOTE — GPIO tasks and events
I2S — Inter-IC sound interface
IPC — Interprocessor communication
KMU — Key management unit
LPCOMP — Low-power comparator
MUTEX — Mutual exclusive peripheral
NFCT — Near field communication tag
NVMC — Non-volatile memory controller
PDM — Pulse density modulation interface
PWM — Pulse width modulation
QDEC — Quadrature decoder
QSPI — Quad serial peripheral interface
RADIO — 2.4 GHz radio
RNG — Random number generator
RTC — Real-time counter
SAADC — Successive approximation analog-to-digital converter
SPIM — Serial peripheral interface master with EasyDMA
SPIS — Serial peripheral interface slave with EasyDMA
SPU — System protection unit
SWI — Software interrupts
TEMP — Temperature sensor
TIMER — Timer/counter
TWIM — I2C compatible two-wire interface master with EasyDMA
TWIS — I2C compatible two-wire interface slave with EasyDMA
UARTE — Universal asynchronous receiver/transmitter with EasyDMA
USBD — Universal serial bus device
VMC — Volatile memory controller
WDT — Watchdog timer
Debug and trace
CTRL-AP - Control access port
CTI - Cross Trigger Interface
TAD - Trace and debug control
Hardware and layout
Pin assignments
Mechanical specifications
Reference circuitry
Package thermal characteristics
Recommended operating conditions
Absolute maximum ratings
Ordering information
Legal notices

The following image shows the application core block diagram.

Application core block diagram — Figure 1. Application core block diagram

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