System efficiency and maximum load considerations

Reverse battery protection for the nPM2100 PMIC

The type of Field-Effect Transistor (FET) used and the battery voltage influence the system efficiency and maximum achieved load current.

Especially when operating at low voltages, the FET's gate-source voltage is not enough to fully turn it on. This results in voltage drops across the transistor, which reduces the overall efficiency.

Input capacitance also has an effect, especially when boost is operating in hysteretic mode. A higher input capacitance results in a lower peak current across the FET during boost activity. This helps in reducing I2 × R losses at the expense of board real estate and BOM cost.

1.5 V battery, 1.8 V VOUT

When an FET is connected in series with the battery and the battery voltage drops to 0.9 V, the maximum current for the boost is 10 mA. This behavior is similar for the PMOS and NMOS used since they have similar characteristics. The following graphs show this behavior.

Figure 1. Load regulation comparison of PMOS with 1.5 V battery, 1.8 V VOUT
Load regulation comparison of PMOS with 1.5 V battery, 1.8 V VOUT
Figure 2. Load regulation comparison for NMOS with 1.5 V battery, 1.8 V VOUT
Load regulation comparison of NMOS with 1.5 V battery, 1.8 V VOUT

Operating close to the minimum supply voltage of 0.9 V impacts system efficiency. When the battery is full, this impact is almost negligible.

Figure 3. Efficiency comparison of PMOS with 1.5 V battery, 1.8 V VOUT
Efficiency comparison of PMOS with 1.5 V battery, 1.8 V VOUT
Figure 4. Efficiency comparison of NMOS with 1.5 V battery, 1.8 V VOUT
Efficiency comparison of NMOS with 1.5 V battery, 1.8 V VOUT

1.5 V battery, 3 V VOUT

With higher boost output voltage, the maximum current with battery voltage at 0.9 V is even lower. This is expected since the conversion ratio is higher. The effect is much smaller when operating at 1.2 V battery voltage or higher. In this state, the boost is able to support most applications.

Figure 5. Load regulation comparison of PMOS with 1.5 V battery, 3 V VOUT
Load regulation comparison of PMOS with 1.5 V battery, 3 V VOUT
Figure 6. Load regulation comparison of NMOS with 1.5 V battery, 3 V VOUT
Load regulation comparison of NMOS with 1.5 V battery, 3 V VOUT
Figure 7. Efficiency comparison of PMOS with 1.5 V battery, 3 V VOUT
Efficiency comparison of PMOS with 1.5 V battery, 3 V VOUT
Figure 8. Efficiency comparison of NMOS with 1.5 V battery, 3 V VOUT
Efficiency comparison of NMOS with 1.5 V battery, 3 V VOUT

3 V battery, 3 V VOUT

When a 3 V battery is used, adding a protection FET has almost no effect on the behavior compared to operating without protection. The protection FET is fully on, and the voltage drop across it is very small.

Figure 9. Load regulation comparison of PMOS with 3 V battery, 3 V VOUT
Load regulation comparison of PMOS with 3 V battery, 3 V VOUT
Figure 10. Load regulation comparison of NMOS with 3 V battery, 3 V VOUT
Load regulation comparison of NMOS with 3 V battery, 3 V VOUT

Like with voltage, adding a protection FET has almost no effect on the efficiency.

Figure 11. Efficiency comparison of PMOS with 3 V battery, 3 V VOUT
Efficiency comparison of PMOS with 3 V battery, 3 V VOUT
Figure 12. Efficiency comparison of NMOS with 3 V battery, 3 V VOUT
Efficiency comparison of NMOS with 3 V battery, 3 V VOUT