PMOS

Reverse battery protection for the nPM2100 PMIC

When the battery is installed in reverse polarity, the gate voltage of the P-Channel Metal-Oxide-Semiconductor (PMOS) Field-Effect Transistor (FET) is high which prevents it from turning on. When the battery is installed in the correct polarity, the gate voltage of the PMOS FET is pulled low, and it switches on.

Figure 1. PMOS connection diagram
Page-1 Sheet.55 nPM2100 nPM2100 vss.1084 Sheet.51 Sheet.52 Sheet.53 Sheet.54 Sheet.56 PVSS PVSS Sheet.57 Sheet.58 Sheet.59 Sheet.60 Sheet.61 Sheet.64 Sheet.65 Sheet.66 Sheet.67 Sheet.68 + + Sheet.69 - - Sheet.70 S S Sheet.71 D D Sheet.72 G G Sheet.73 pmosa.1116 Sheet.75 nmos.105 Sheet.77 Sheet.78 Sheet.79 Sheet.80 Sheet.81 Sheet.82 Capacitor.1127 Sheet.84 Sheet.85 Sheet.86 Sheet.87 Sheet.88 Sheet.90 Sheet.92 VBAT VBAT R-node.1051 R-node.94 R-node.95 R-node.96

When the PMOS FET is used, a voltage drop appears between the drain and source. The drop is equal to RDS(on) × IBAT, where RDS(on) is the drain-source on-resistance. The gate itself has a very high impedance, and virtually no extra quiescent current is drawn through the gate connection.

For performance testing, an Analog Power AM2305PE FET was used since its gate-source voltage is low enough, its current rating is sufficient for the nPM2100 application, and its RDS(on) is low enough to allow a low voltage drop across the FET in normal operation. Also, its package size is SOT-23, which is relatively small.