NMOS

Reverse battery protection for the nPM2100 PMIC

When the battery is installed in reverse polarity, the gate voltage of the N-Channel Metal-Oxide-Semiconductor (NMOS) Field-Effect Transistor (FET) is low which prevents it from turning on. When the battery is installed in the correct polarity, the gate voltage of the NMOS FET goes high, and it switches on.

Figure 1. NMOS connection diagram
Page-1 vss.1035 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 nPM2100 nPM2100 Sheet.12 VBAT VBAT Sheet.13 PVSS PVSS Sheet.14 Sheet.15 Sheet.16 Sheet.17 Sheet.18 R-node.1051 R-node.1052 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 + + Sheet.26 - - nmosa.1073 nmos.105 Sheet.29 Sheet.30 Sheet.31 Sheet.32 Sheet.33 S S Sheet.34 D D Sheet.35 G G Sheet.36 Sheet.37 Capacitor.1136 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 R-node.1142 Sheet.45 R-node.1144

When the NMOS FET is used, a voltage drop appears in the ground return path. The drop is equal to RDS(on) × IBAT, where RDS(on) is the drain-source on-resistance. The gate itself has a very high impedance, and virtually no extra quiescent current is drawn through the gate connection.

For performance testing, an Analog Power AM2336N FET was used since its gate-source voltage is low enough, its current rating is sufficient for the nPM2100 application, and its RDS(on) is low enough to allow a low voltage drop across the FET in normal operation. Also, its package size is SOT-23, which is relatively small.